Showing papers on "Snapback published in 2007"

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

Abstract: SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.

Obtaining TLP-like information from an HBM simulator

Abstract: Obtaining TLP-type data from properly instrumented HBM systems is demonstrated. Parameters similar to those extracted by TLP are measured from HBM pulses. The new concept of "DUT snapback impedance" is introduced to explain DUT response to 1500Omega HBM pulses and various impedance TLP systems. Observed stresses with HBM, not present in TLP, may account for some HBM-TLP miscorrelations.

Electrostatic discharge protection device for pad and method and structure thereof

Abstract: An ESD protection device for a pad includes an adjusting circuit, a snapback element and a control circuit. The adjusting circuit includes a silicon controlled rectifier (SCR) coupled to the pad. The SCR includes a first diode. The snapback element is coupled to a first N pole of the first diode when a second diode is not used, and is coupled to a second N pole] of the second diode when the second diode is used. The control circuit is coupled to the first N pole. In a normal operation mode, the control circuit provides a first voltage to the first N pole so that the first N pole collects a plurality of charges and the SCR is turned off. In an ESD mode, the control circuit does not provide the first voltage to the first N pole so that the first N pole does not collect the charges.

An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

Abstract: A new silicon-controlled rectifier (SCR) is proposed and realized in a 0.35-mum/3.3-V fully salicided BiCMOS process for electrostatic-discharge (ESD) applications. Without using an external trigger circuitry, the unassisted SCR has a trigger voltage as low as 7 V to effectively protect deep-submicrometer MOS circuits, a holding voltage higher than the supply voltage to minimize transient influence and avoid latch-up issue, and a second snapback current density exceeding 60 mA/mum to provide robust ESD-protection solutions.

Measurements of the Persistent Current Decay and Snapback Effect in Tevatron Dipole Magnets

Abstract: A systematic study of the persistent current decay and snapback effect in the fields of Tevatron accelerator dipoles was performed at the Fermilab Magnet Test Facility (MTF). The decay and snapback were measured under a range of conditions including variations of the current ramp parameters and magnet operational history. The study has mostly focused on the dynamic behavior of the normal sextupole component. In addition, the paper presents the persistent current effects observed in the other allowed field harmonics as well. The results provide new information about the previously observed "excess" decay during the first several seconds of the sextupole decay during injection and the correlation between the snapback amplitude and its duration.

Active Control of the Triggering Characteristics of NPN BJT, BSCR and NLDMOS-SCR Devices

Abstract: This study presents a new solution for ESD protection of high-voltage and high-speed pins in power analog circuits, such as voltage switching regulators. A mixed device-circuit ESD solution is validated experimentally using transmission line pulse measurements. It is demonstrated that the triggering characteristics of both bipolar and MOS ESD devices can be successfully controlled as a function of operation mode in a large voltage range using an active circuit and control electrodes. An example of an active circuit to control the triggering characteristics of the ESD devices is presented. A practical implementation is verified for 50 V NPN BJT, Bipolar SCR and LDMOS-SCR snapback ESD devices. The advantage of the proposed solution over snapback ESD devices triggered by avalanche or displacement current is discussed for high-speed power analog applications.

Diode-based ESD concept for DEMOS protection

Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

BVDII Enhancement with a Cascode DMOS

Abstract: Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.

Erase pin protection in EEPROM using active snapback ESD device with positive feedback and shutdown

Abstract: In an ESD protection circuit for an EEPROM erase pin a snapback device is provided for discharging high ESD currents, whereas the snapback device is operated in active mode during low voltage electrical overstress and to discharge post ESD event current by connecting an RC circuit over the control electrode of the snapback device. In order to handle high voltage normal operating conditions the snapback device is deactivated once VDD is applied by pulling the control electrode to ground using a VDD controlled switch.

An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies

Abstract: Second breakdown phenomenon (It2) in drain extended NMOS (DENMOS) which is associated with complex triggering of the parasitic BJT is relatively less understood. We present experiments and models to understand the physics of snapback in DENMOS in nanometer scale technologies. Avalanche injection phenomenon at the drain contact has been analyzed for a 90 nm DENMOS transistor under high current stressing

Numerical computation of orbits and rigorous verification of existence of snapback repellers

Abstract: In this paper we show how analysis from numerical computation of orbits can be applied to prove the existence of snapback repellers in discrete dynamical systems. That is, we present a computer-assisted method to prove the existence of a snapback repeller of a specific map. The existence of a snapback repeller of a dynamical system implies that it has chaotic behavior [F. R. Marotto, J. Math. Anal. Appl. 63, 199 (1978)]. The method is applied to the logistic map and the discrete predator-prey system.

A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism under ESD Conditions

Abstract: We present for the first time, analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of 'thermal runaway' under ESD conditions. The estimated It2 value from transient simulations has been correlated with the quasi-steady TLP data. A new regenerative bipolar turn-on induced failure model has been proposed and corroborated with experimental observations and failure analysis. We have also investigated the current crowding mechanism to understand the improvement in It2 value under gate and substrate biasing.

Floating gate structure with high electrostatic discharge performance

Abstract: Systems and methods for floating gate structures with high electrostatic discharge performance. In one embodiment, a semiconductor structure includes a floating field gate device. The floating field gate device includes an embedded diode characterized as having less temperature dependence than a Zener diode. The breakdown voltage of the embedded diode is greater than an operating voltage of an associated integrated circuit and a snapback trigger voltage of the embedded diode is lower than a breakdown voltage of the semiconductor structure.

A Study of Snapback and Parasitic Bipolar Action for ESD NMOS Modeling

Abstract: A study has been done on the snapback and parasitic bipolar action for modeling ESD NMOS in this paper. A DC model for ESD NMOS is provided, which includes a MOS transistor extracted from BSIM 3V3, a bipolar transistor for parasitic effect, substrate resistance and series resistance. Equations for modeling the high current behavior of NMOS transistor have been developed. Extraction methodology for obtaining the bipolar parameters is given. Simulation results are presented and compared to the testing data for 0.6 um NMOS.

ESD protection circuit with a low snapback voltage that is protected from fast non-ESD voltage spikes and ripples

Abstract: A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.

Effects of Background Doping Concentration on ESD Protection Properties of High Voltage Operation Extended Drain N-Type MOSFET Device

Abstract: In this study, the effects of background doping concentration (BDC) on the electrostatic discharge (ESD) protection performances of a high voltage operating extended drain N-type MOSFET (EDNMOS) device were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that a good ESD protection performance can be realized in terms of the EDNMOS device by properly controlling its BDC.

S-shaped negative differential resistance modeling in electro-thermal simulation of phase-change memory programming

Abstract: Electro-thermal modeling has been commonly employed to model the RESET (crystalline-to-amorphous) transition in phase-change memory devices. However, to fully model the SET (amorphous-to-crystalline) transition, it is required to comprehend the S-shaped negative differential resistance (NDR) that precedes the phase transition, as input current is ramped up. Carrier dynamics on nanosecond time scales have been invoked to model the "snapback" phenomenon. To build S-shaped NDR models within commercial electrothermal simulation packages, we consider various resistivity models which may be calibrated to provide a good flt with experimental data. We find that regardless of the model, it is necessary to include a constant offset in the resistivity formula, in order to consistently obtain the observed ON state portion of the l-V curve.

Method and apparatus for electrostatic discharge protection having a stable breakdown voltage and low snapback voltage

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region (20) having doped regions is formed on a substrate (102), interconnects (140, 142) contacting the dynamic region (20). The dynamic region (20) includes an Nwell region (104), a Pwell region (106) and shallow diffusions (110, 112, 114, 116, 118), defining a PNP region (346), an NPN region (348) and a voltage Breakdown region. In an aspect, the Nwell region (104) includes a first N+ contact (110), a first P+ contact (112) and an N+ doped enhancement (114), while the Pwell region (106) includes a second N+ contact (116), a second P+ contact (118) and a P+ doped enhancement (122). The N+ doped enhancement (114) contacts the P+ doped enhancement (122) forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction (652). Independent control is provided over breakdown voltage, NPN critical voltage, NPN critical current and PNP critical current, by varying doping levels, widths and positioning of various doping regions.

ESD Protection of Fast Transient Pins in Bipolar Processes

Abstract: The results of a comparative analysis between transient triggered and voltage referenced ESD power clamps are presented. Different architectures with both external and the internal breakdown voltage reference techniques are studied leading towards both optimal snapback characteristics and a small footprint ESD protection solution for power management applications. The physical mechanism of ESD snapback operation is discussed in terms of the classical understanding of avalanche-injection conductivity modulation in a bipolar transistor. The advantage of an internal Zener diode solution over both an enhanced Zener and a BVCER clamp is demonstrated.

Circuit configurations to reduce snapback of a transient voltage suppressor

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

Analysis of design strategies for RF ESD problems in CMOS circuits

Abstract: This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip.

Characteristics of an Extended Drain N-Type MOS Device for Electrostatic Discharge Protection of a LCD Driver Chip Operating at High Voltage

Abstract: We have evaluated the effects of the background doping concentration (BDC) on electrostatic discharge (ESD) protection by using an extended drain N-type metal oxide semiconductor (EDNMOS) field effect transistor device operating at high voltage. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both good ESD protection and latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC. As a result of transmission line pulse (TLP) test, an ESD current immunity level of 5.08 mA/um and a good linear scaling behavior were achieved for a multi-finger-type device.

Lateral resurf NPN with high holding voltage for ESD applications

Abstract: In an ESD protection circuit an NPN BJT snapback device is provided with high breakdown voltage by including a RESURF region or by forming a PIN diode in the BJT. Holding voltage is increased by forming a sub-collector sinker region with the desired configuration.

A Microscopic Understanding ofNanometer Scale DENMOS Failure Mechanism underESDConditions

Abstract: II.Irreversible It2Phenomenon (inNMOS) Vs Wepresent forthefirst time, analysis ofirreversible snapback Irreversible Strong Snapback (inDENMOS) caused duetotheregenerative n-p-nturn-on ina DENMOS Roleoftheparasitic bipolar turn-on (during snapback) under through acritical understanding of'thermal runaway' under ESD ESDevents hasbeenanenigma --while itisknowntoimprove the conditions. Theestimated 1t2value fromtransient simulations hasIt2performance ina NMOS;itseverely degrades theESD beencorrelated withthequasi-steady TLP data.A new

N-Type Extended Drain Silicon Controlled Rectifier Electrostatic Discharge Protection Device for High-Voltage Operating Input/Output Applications

Abstract: An electrostatic discharge (ESD) protection device, the so-called N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high-voltage input/output (I/O) applications. A conventional NEDSCR device shows typical silicon controlled rectifier (SCR)-like characteristics with a high current immunity level. However, its extremely low snapback holding voltage and low on-resistance cause a linearity problem in the current immunity level, which obstructs adopting this device as an ESD protection device. Moreover, it may cause a latch-up problem during a normal operation. Our simulation analysis results that these disadvantageous NEDSCR device characteristics are cured by appropriate junction/channel engineering. Adding a P-type counter pocket source (CPS) implant enclosing source N+ diffusion is proven to increase the snapback holding voltage and on-resistance of the NEDSCR device, realizing an excellent ESD protection performance and a high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.