Showing papers on "Snapback published in 2008"

Low side Zener reference voltage extended drain SCR clamps

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Abstract: Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current I t2 , holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-to-gate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.

Dynamic Turn-On Mechanism of the n-MOSFET Under High-Current Stress

Abstract: In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of ldquoself-consistent effect,rdquo i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (ID). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with ID instead of 0.6-0.8 V and independent of ID as reported in early literatures.

Lateral PNP BJT ESD protection devices

Abstract: A new high voltage lateral PNP with sufficient current density for small footprint ESD protection is experimentally demonstrated in a 40 V drain-extended CMOS process. It is found that a lateral PNP device can exhibit snapback behavior similar to that characteristically associated with NPN-based ESD clamps. The mechanism leading to this effect is further studied for PNPs in a BiCMOS process using physical process and device simulation. This analysis reveals that the formation of a quasi-neutral electron-hole plasma in the N-base drift region reduces the base electric field and thus the emitter-collector voltage drop, explaining the observed behavior. The advantage of this lateral PNP is to provide local ESD protection that is robust against transient latch-up.

Electrostatic discharge power clamp with improved electrical overstress robustness

Abstract: An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by the RC triggering device during an ESD event, wherein the SCR, when activated, acts as a power rail voltage clamp; and a field effect transistor (FET) coupled between the RC triggering device and the SCR, wherein the FET serves as an integrated part of the RC triggering device that triggers the SCR during the ESD event; and wherein the FET also operates in a snapback mode to trigger the SCR during an EOS event that is slower in comparison to the ESD event such that the EOS event would not otherwise cause triggering of the SCR via the RC triggering device itself.

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Abstract: In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mum 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.

Extreme voltage and current overshoots in HV snapback devices during HBM ESD stress

Abstract: The turn-on behavior of high voltage ESD devices is studied during HBM ESD stress. Two phenomena are experimentally observed for two different HV processes and several device architectures: a voltage overshoot up to two times of the TLP triggering voltage, and a current overshoot several times the nominal HBM current.

A novel ESD super-clamp structure for TVS applications

Abstract: This paper presents a new ESD clamp structure for transient voltage suppressor (TVS) applications that combines the advantages of avalanche diode and bipolar transistor clamps. The device structure consists of a non-snapback avalanche diode triggered vertical NPN transistor. The avalanche diode provides the fast trigger and current conduction path at low currents, while the vertical NPN bipolar transistor turn-on provides alternate low resistance path for current conduction at high currents. The snapback in the IV characteristics is minimized by matching the avalanche diode breakdown voltage VBD and the vertical NPN transistor open base collector-emitter breakdown voltage, BVCEO- Measurements on fabricated devices show consistent results with the theory. The TVS has low leakage currents (< 25 nAmps), negligible snapback in the output characteristics (<0.5 Volts) and excellent clamping voltage at high currents (13.1 Volts @ 30 Amps of TLP current). The presence of low doped base region also results in 35 % decrease in the TVS capacitance.

Design Analysis of a Novel Low Triggering Voltage Dual Direction SCR ESD Device in 0.18μm Mixed Mode RFCMOS Technology

Abstract: A novel SCR on-chip ESD device is proposed to protect IC chips against ESD stressing in two opposite directions.The triggering voltages of four types of dual direction SCRs (DDSCR) are compared and analyzed.pMOS or nMOS are embedded into the structures to adjust their triggering voltages.Both MOSFETs embedded DDSCRs have tunable triggering voltage,low DC leakage (~pA),and fast turn on speed snapback I-V characteristics without latch-up problem.It achieves high ESD performance of ~94V/μm.The new ESD protection devices are area efficient and can reduce the parasitic effects significantly.

Mechanism of Reverse Snapback on I-V Characteristics of Power SITHs with Buried Gate Structure

Abstract: The reverse snapback phenomena (RSP) on I-V characteristics of static induction thyristors (SITH) are physically researched. The I-V curves of the power SITH exhibit reverse snapback phenomena, and even turn to the conducting-state, when the anode voltage in the forward blocking-state is increased to a critical value. The RSP I-V characteristics of the power SITH are analyzed in terms of operating mechanism, double carrier injection effect, space charge effect, electron-hole plasma in the channel, and the variation in carrier lifetime. The reverse snapback mechanism is theoretically proposed and the mathematical expressions to calculate the voltage and current values at the snapback point are presented. The computing results are compared with the experiment values.

ESD Protection of NDMOS in 0.18μm High-Voltage CMOS Technology for Automotive Applications

Abstract: The snapback trigger voltage of the NDMOS in a 0.18 μm automotive smart power technology is strongly reduced at large gate bias. This behavior of the deep-submicron multi-resurf NDMOS, which makes its ESD protection difficult and limits its electrical safe operating area, and the influence of various device modifications are investigated by TCAD simulation. SCR-based ESD protection schemes for I/O and power supply protection are presented. For supply protection the SCR is modified to increase its holding voltage. The ability to protect the NDMOS at non-zero gate bias is discussed.

Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation

Abstract: An enhancement to the modeling of the ‘snapback’ in MOS transistors for ESD simulation is presented. The new model uses industry standard models and includes all major physical effects characteristics of snapback. The MOS snapback model is enhanced by partitioning the Drain and Source junctions so that only a portion of them is included in the parasitic BJT. The comparison of simulation and measured data of a Grounded-Gate NMOS shows good agreement for both positive and negative drain voltage stresses. Simulation of the base current of the parasitic bipolar shows significant improvement as well.

Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology

Abstract: In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Abstract: An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

Small footprint trigger voltage control circuit for mixed-voltage applications

Abstract: An ESD protection solution for high voltage input pins consists of a snapback ESD device controlled by a driver circuit that is optimized for performance, small footprint and specific compatibility features. Several control circuits geared towards area minimization are presented, followed by experimental validation of the circuits.

Reliability of NLDMOS transistors subjected to repetitive power pulses

Abstract: The failure mechanisms for NLDMOS transistors subjected to rectangular power pulses are investigated. The study confirms by measurement and simulation that the transistors survive single power pulses up to an energy that causes snapback at a critical temperature. However, devices can fail due to large thermal-mechanical stress and metal migration when subjected to repetitive power pulses of significantly smaller energy. The failure mechanism is confirmed by physical analysis then a Coffin-Manson metal fatigue model is applied to predict transistor reliability.

Active ESD protection design methodology for DC/DC converters

Abstract: A simple, area and power-loss efficient, portable and robust ESD protection method for DC/DC converters is presented The method is based on MOS transistors operating in normal mode, replacing the snapback based design methods Measurement results of a prototype fabricated on silicon showed good agreement with simulation and are reported

Design, Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier (scr)-based Devices For Electrostatic Discha

Abstract: Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core…

Snapback and overprogramming modeling using finite-element electrothermal simulation

Abstract: We present a new model for the simulation of negative differential resistance (?snapback?) in a phase-change memory cell using an electrothermal finite-element iterative calculation implemented in ANSYS. This model improves upon our previous models by applying a double Arrhenius temperature-dependent resistivity for the amorphous chalcogenide, and a JMAK (n=3.5) model to describe the phase-change kinetics. As a result, the model captures the possibility of partial crystallization during typical pulsed heating conditions, a crucial factor in determining the abruptness of snapback. In addition to fitting our experimental data, the model is capable of predicting and characterizing the onset of overprogramming. Overprogramming occurs when the process of crystallizing some parts of the initially amorphous region leads to other parts heating above the melting point, leading to a remnant amorphous portion that limits the reduction of the cell?s resistance. The paper also explores the impact of initial amorphous size as well as the presence of a defect breaking the symmetry of the amorphous hemisphere.

Semiconductor device having esd protecting element

Abstract: PROBLEM TO BE SOLVED: To provide an ESD (Electro Static Discharge) protecting element of a semiconductor device having a structure actualizing desired ESD resistance without impairing linearity of capacitance variation of a variable capacitance element. SOLUTION: The variable capacitance element of an oscillation circuit is constituted by having a first N type region enclosed with an element isolation region, a first high-density P type region below the element isolation region, a first P type region contacting the first N type region to form a PN junction, and a second N type region formed opposite the first N type region with the element isolation region interposed, and connecting the first P type region to a ground potential and the first N type region to a control voltage. The first N type region, first high-density P type region, and second N type region constitute a snapback transistor as an ESD protecting element by connecting the second N type region to the ground potential. COPYRIGHT: (C)2009,JPO&INPIT

Variable Lateral Silicon Controlled Rectifier as an ESD Protection

Abstract: Abs tract: - The Variable lateral Silicon Controlled Rectifier (VLSCR) is a SCR based structure with the possibility to tune I-V snapback characteristics. This effect is important for an ESD (electrostatic discharge) protection design. The ESD protection structures act as a protection of integrated circuits against parasitic electrostatic discharge. Among often used structures belong structures having snapback type of I-V characteristic. Typical is a gate-grounded NMOS transistor [3] or a SCR [3]. This text is dealing with the VLSCR structure which enables I-V snapback characteristics tuning according to the application demand. Simulated technology was 0.5µm CMOS very high voltage (VHV Integrated Circuits). Measurement was done in 1.5 µm BiCMOS process.

Holding voltage adjustable silicon controlled rectifier

Abstract: Holding voltage adjustable Silicon Controlled Rectifier (HVASCR) is a SCR with possibility to tune the holding voltage. The HVASCR structure forms good ESD (electrostatic discharge) protection. Such structures act as a protection of integrated circuits against parasitic electrostatic discharge. The use of such structures provides ICs robustness against ESD. Typical ESD cell is gate grounded NMOS transistor or SCR. The HVASCR enables tuning of I-V snapback characteristics. Simulated technology was CMOS very high voltage (VHVIC) and measurement was done for samples manufactured in 1.5 mum BiCMOS.

On chip electrostatic discharge protection for MEMS gas sensor system

Abstract: An on-chip electrostatic discharge(ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems(MEMS)-based embedded sensor(ES) system-on-a-chip(SoC).The ESD protection scheme is implemented using ground-referenced multifinger thyristor-type devices optimized for 1) the input/output(I/O) protection,2) the power supply clamp,and 3) the internal sensors' electrodes during the micromachining process.A multiply finger layout scheme was also developed to the ESD protection level under the constraint of chip size.The ESD protection design methodology was tested and verified at both the device and SoC levels,and its effectiveness and robustness have been illustrated.Experimental results showed that the SoC passed a 4.1 kV Human Body Model ESD stress with no latchup induced and a very low leakage current of 10-10 A.