Showing papers on "Snapback published in 2009"

Transient voltage suppressor (TVS) with improved clamping voltage

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.

Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node

Abstract: Technology scaling data are presented based on 65nm, 45nm, and the 32nm High-K, metal gate process. Thin oxide NFET parasitic bipolar snapback and gate dielectrics breakdown voltages decrease to 3.2V and 3.6V, respectively. The top concern is to achieve adequate voltage clamping at I/O pads. Continuous improvement in ESD device failure currents per area is found. Vertical metal wiring schemes are needed to overcome wiring resistance challenges.

Modeling IC Snapback Characteristics Under Electrostatic Discharge Stress

Abstract: This paper presents a novel technique for modeling the electrostatic discharge snapback phenomenon in integrated circuits (ICs). The macromodel is built using standard components: BSIM3v3.2 model for the MOSFET, a bipolar transistor modeled by Mextram 504.7, and a substrate resistor. The IC under test is characterized by its die and package impedance. The model should allow easier simulation program with IC emphasis implementation, high simulation speed, less convergence issues, and wider availability of a gate-grounded n-type MOSFET protection device. Our model determines the interaction between the protection device and the internal circuitry of the IC. The model parameters are extracted with MATLAB script. Simulation results are compared with transmission-line pulsing measurement for a voltage regulator NCV4949 and a controller area network transceiver TLE6250G.

Over-limit electrical condition protection circuits for integrated circuits

Abstract: Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

System level and hot plug-in protection of high voltage transient pins

Abstract: A new high holding voltage lateral PNP device is experimentally demonstrated in a 40 V drain-extended CMOS process, followed by a new compact PNP-SCR device-level solution utilizing a two-stage snapback. The advantage of these lateral DeMOS-based devices is the capability to provide local ESD protection that is robust against transient latch-up for pins with system level, hot swap, and hot plug-in requirements.

Electrostatic discharge protection circuit for integrated circuits

Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) that provides ESD protection during an ESD event is disclosed. The electrostatic discharge (ESD) protection circuit includes a first electrostatic discharge (ESD) protection component and a second electrostatic discharge (ESD) protection component coupled in series to the first electrostatic discharge (ESD) protection component. A snapback holding voltage of the electrostatic discharge protection circuit is greater than the operating voltage of the electrostatic discharge protection circuit and a snapback trigger voltage of the electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said integrated circuit.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Abstract: Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-? transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

2.5-Dimensional simulation for analyzing power arrays subject to ESD stresses

Abstract: A new simulation-based methodology for analyzing the ESD performance of snapback multi-finger power arrays subject to ESD stress is developed and presented. The methodology utilizes a combination of a newly available 2.5-dimensional netlist extraction tool, ESD cell snapback compact model, and standard simulation CAD tools. Simulated snapback behavior and current distribution of power cells are demonstrated.

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Abstract: Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.

Electrical overstress protection circuit

Abstract: A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device

Abstract: The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.

Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region

Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Analysis of Snapback Phenomena in VDMOS Transistor having the High Second Breakdown Current: A High ESD Mechanism Analysis

Abstract: We proposed the balanced vertical double - diffused MOS (B-VDMOS) transistor. The B-VDMOS transistor is not destroyed by avalanche breakdown and acquires the high second breakdown current. Owing to the high second breakdown current, the B-VDMOS transistor has high electrostatic discharge (ESD) robustness. This paper presents the mechanism of the snapback phenomena and clarifies the cause that the B-VDMOS transistor has the high second breakdown current. We find the cause that current does not become concentrated even after avalanche breakdown in the B-VDMOS transistor. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits

Abstract: The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 μm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.