Showing papers on "Snapback published in 2010"

Silicon-Controlled Rectifier Stacking Structure for High-Voltage ESD Protection Applications

Abstract: Latchup immunity is a challenging issue for the design of power supply clamps used in high-voltage electrostatic discharge (ESD) protection applications. While silicon-controlled rectifiers (SCRs) are highly robust ESD devices, they are traditionally not suited for high-voltage ESD due to their inherent low holding voltage and, thus, vulnerability to latchup. In this letter, a novel SCR stacking structure with an extremely high holding voltage, very small snapback, and acceptable failure current has been developed. The new and existing high holding voltage ESD devices are also compared to demonstrate the advancement of this work.

A new way to alleviate the RC IGBT snapback phenomenon: The Super Junction solution

Abstract: In this paper we present a new device, the 3.3kV semi-SuperJunction Reverse Conducting Insulated Gate Bipolar Transistor that can help to alleviate the voltage snapback of the Reverse Conducting IGBT while we achieve significant improvement in the on-state vs switching trade-off performance of the IGBT. The introduction of the SuperJunction structure in the drift region of the RC IGBT reduces the effective on-state resistance under unipolar current conduction. This ultimately affects the voltage snapback value as well as the reverse recovery of the diode while turn off.

Snapback and Postsnapback Saturation of Pseudomorphic High-Electron Mobility Transistor Subject to Transient Overstress

Abstract: The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.

Reverse-conducting insulated gate bipolar transistor with an anti-parallel thyristor

Abstract: An IGBT with a novel reverse conduction structure is presented and first demonstrated by numerical simulations. As opposed to the standard anti-parallel diode existent in power MOSFETs and conventional reverse conducting IGBTs, here we propose an anti-parallel reverse-conducting thyristor with a very low break-over voltage. The structure includes a narrow-base npn BJT to realise an embedded thyristor which acts like a diode in its on-state conduction. In addition, the narrow-base npn BJT helps to mitigate the snapback issue which usually appears in the conventional RC-IGBTs. The new device also feature a number of floating N+ dots in the N-buffer layer to adjust the device static and switching performance without the need of cumbersome lifetime killing processes. Simulation results have shown that the new device can achieve a low on-state voltage of 1.3 V in forward conduction and 1.2 V in reverse conduction, for 600-V blocking rating, coupled with fast switching performance.

Non-snapback scr for electrostatic discharge protection

Abstract: An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99). By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage).

A failure levels study of non-snapback ESD devices for automotive applications

Abstract: Snapback ESD devices suffer from increasing danger when the protected ICs experience ESD events in powered up states. To ensure more reliable ESD protections, non-snapback ESD structures are gaining more importance in the field of automotive ESD design. Two types of on-chip non-snapback ESD devices, pn-diodes and active FET structures are investigated in this work regarding their failure levels. Characteristics of the ESD devices as well as electrical SOA of an nLDMOS are evaluated and discussed in detail with TCAD electro-thermal simulation, SPICE circuit simulation and mainly TLP measurements. Comparison of the efficiency of different ESD protections considering ESD window is also given, delivering the basic idea of choosing the right ESD devices in automotive applications.

Integrated circuit, electronic device and esd protection therefor

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry (100) arranged to provide ESD protection to an external terminal (102) of the integrated circuit. The ESD protection circuitry (100) comprises: a thyristor circuit (200, 204) comprising a first bipolar switching device (200) operably coupled to the external terminal (102) and a second bipolar switching device (204) operably coupled to another external terminal (104), a collector of the first bipolar switching device (200) being coupled to a base of the second bipolar switching device (204) and a base of the first bipolar switching device (200) being coupled to a collector of the second bipolar switching device (204). A third bipolar switching device (214) is also provided and operably coupled to the thyristor circuit (200, 204) and has a threshold voltage for triggering the thyristor circuit (200, 204), the threshold voltage being independently configurable of the thyristor circuit (200, 204). The first and second switching devices (200, 204) are arranged so as to provide, when in use, a bidirectional snapback characteristic and a snapback voltage associated therewith.

Ultra high voltage GaN ESD protection device

Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Robust high current ESD performance of nano-meter scale DeNMOS by source ballasting

Abstract: “Strong Snapback” in DeNMOS transistors leads to weak ESD performance which is often represented by low It2 and strong die to die dependence. We report here the first experimental evidence that this can be controlled with introduction of source-resistance Rs. A new microscopic model has been analyzed to understand the physics of strong snapback and explain the experimental observations. Impact of current crowding phenomenon and role of adding a resistor across the source and ground has been broadly addressed in this paper. Also the current crowding phenomenon has been macroscopically modeled and a circuit model has been established.

Shared electrostatic discharge protection for integrated circuit output drivers

Abstract: A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material (205). The system includes a contact ring (225, 325, 420) coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid (385, 460) of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of R sub (substrate resistance 275 and 280) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of R sub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.

Engineering fully silicided large MOSFET driver for maximum It1 performance

Abstract: Simultaneous optimization of LDD and Anti-punch-through implant conditions for ESD performance of very large width silicided output driver nMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulse width are detailed.

High-voltage LDMOS device

Abstract: The invention discloses a high-voltage LDMOS device The high-voltage LDMOS device comprises a grid (22) and a drain (23), wherein the drain (23) is arranged in a low-voltage N well (132) and the low-voltage N well (132) is arranged in a high-voltage N well (122); a part, above the high-voltage N well (122), between the grid (22) and the drain (23) is provided with silicon oxide (161); polycrystalline silicon (171) is arranged above the silicon oxide (161); and the two sidewalls of each of the silicon oxide (161) and the polycrystalline silicon (171) are provided with a silicon nitride sidewall (18) respectively On one hand, the high-voltage LDMOS device can avoid the poor hot carrier effect and the Snapback breakdown of the device caused by a 'bird beak' structure of the conventional high-voltage LDMOS device; and on the other hand, 'field plate effect' can be achieved and electric field strength in the vicinity of a PN junction of the drain (23) is reduced, so that high breakdown voltage can be satisfied

Electrostatic discharge protecting equipment of connection pad and its method and structure

Abstract: The invention relates to a static discharge protective device of a bond pad, which comprises a regulating circuit, a snapback component and a control circuit. The regulating circuit comprises a silicon controlled rectifier coupled to the bond pad. The silicon controlled rectifier comprises a first diode. Under the circumstance of not utilizing the first diode, the snapback component is coupled tothe N pole of the first diode; under the circumstance of utilizing the first diode, the snapback component is coupled to the N pole of a second diode. The control circuit is coupled to the N pole of the first diode, under the mode of normal operation, the control circuit is used to provide a first voltage to the N pole of the first diode to lead the N pole of the first diode to collect a pluralityof charged carriers, and to lead the silicon controlled rectifier not to be turned on, under the mode of static discharge, the control circuit does not provide the first voltage to the N pole of thefirst diode to lead the N pole of the first diode not to collect the charged carriers.

A quantitative inquisition into ESD sensitivity to strain in nanoscale CMOS protection devices

Abstract: This paper presents the first detailed experimental investigation together with theoretical analysis of the impact of strain on ESD robustness in nanometer scale planar CMOS protection devices in both bulk and SOI technologies. Gated diodes as well as NMOS devices in both gate-grounded (GG) and gate-tied-high (GH) configurations are investigated. It is shown that the ESD sensitivity to strain can vary substantially depending on whether the stressed devices are bulk or SOI, and on the mode in which they are stressed. Modulation of snapback region due to strain and its impact on device electrical stability, competing requirements for ballasting and strain effects, strain non-uniformity induced performance reduction, as well as comparative analysis of ESD vs DC performance improvement are discussed in detail. Increase in ESD robustness of about 20% is obtained for bulk gated-diodes and SOI GG-NMOS, due to strain engineering. On the other hand, it is shown that high tensile strain can influence the bipolar action of bulk GG-NMOS by enhancing the snapback behavior. Insights are provided in this work to specify guidelines in terms of device configuration, operation principle and type of strain in order to leverage maximum improvement from strain engineering.

ESD protection of NMOS device at different gate bias

Abstract: In salicided sub-micron CMOS technology,the electrostatic discharge (ESD) performance of NMOS device as the self-protected output buffer at uncertain gate bias was analyzed.NMOS device structures for ESD protection were designed and fabricated in a 0.35 μm CMOS process.Their ESD abilities were measured by a transmission line pulse (TLP) testing system at different gate bias.With ISE-TCAD,the electric field density distribution of the device at different gate bias was shown by transient simulation.The results show that the gate bias can degrade the second breakdown current because of more current flow at the surface of NMOS device.When designing the snapback based gate coupled NMOS ESD protection device,the RC time constant of trigger-assisting circuit should be controlled around 50 ns.

Physical effect on transition from blocking to conducting state of barrier-type thyristor

Abstract: The transition of the barrier-type thyristor (BTH) from blocking to conducting-state occurs between two entirely contrary physical states with great disparity in nature The physical effects and mechanisms of the transition are studied in depth The features of the transition snapback point are analyzed in detail The transition snapback point has duality and is just the position where the barrier is flattened It has a significant influence on the capture cross-section of the hole and high-level hole lifetime, resulting in the device entering into deep base conductance modulation The physical nature of the negative differential resistance segment I−V characteristics is studied It is testified by using experimental data that the deep conductance modulation is the basic feature and the linchpin of the transition process The conditions and physical mechanisms of conductance modulation are investigated The related physical subjects, including the flattening of the channel barrier, the buildup of the double injection, the formation of the plasma, the realization of the high-level injection, the elimination of the gate junction depletion region, the deep conductance modulation, and the increase in the hole's lifetime are all discussed in this paper

Investigation of ESD second breakdown TCAD simulation

Abstract: This paper presents the methodology to obtain the snapback curves and second breakdown point of an ESD stressed device through TCAD simulation. This method allows an excellent ESD simulation convergence and then good ESD prediction with a significantly reduced computation time. One 0.5um CMOS technology has been simulated for experimental support.

To achieve a novel weak snapback characteristic in the high voltage nLDMOS

Abstract: A drain-side engineering to LDMOS by doping concentration and length modulations of the N-type adaptive layer to obtain weak snapback characteristic nLDMOS are presented in this work It's a novel method to reduce trigger voltage(V t1 ) and to increase holding voltage(V h ) These efforts will be very suitable for the HV power management IC applications Meanwhile, in this work, we will discuss trigger voltage, holding voltage and R on resistance distribution of these novel HV nLDMOS devices

Self protected snapback device driven by driver circuitry using high side pull-up avalanche diode

Abstract: In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices.

Transient voltage suppressor (TVS) with improved clamping voltage

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.

Advanced Simulation for ESD Protection Elements

Abstract: Electrostatic discharge (ESD) failure is one of the most important causes of reliability problems, therefore the design and optimization of ESD devices have to be done. To achieve very short time to market and reduce the development effort, one tries to make use of the benefit of simulation tools. However, due to the complex physical mechanism of ESD events and the hard mathematic calculation in the snapback region, simulation of the I-V characteristic of ESD protection devices has been proved to be difficult. This chapter aims at providing a systematic way to ESD simulation, including the process simulation, device simulation and circuit level simulation. Process/device simulation offers an effective way to evaluate the performance of ESD protection structures. However, to prevent the injury of ESD, protection circuits are used sometimes. Therefore circuit level simulation is needed. There are several process/device simulation tools in the world, the most widely used of which include Tsuprem4/Medici, Athena/Atlas and Dios/Mdraw/Dessis. Tsuprem4, Athena and Dios are process simulators, while Medici, Atlas and Dessis are device simulators. Mdraw is an independent mesh optimization tool, and the similar functions are integrated in device simulation tools, such as Medici and Atlas. The process and device simulation methods introduced in the following will be based on Dios/Mdraw/Dessis, except for the mixed-mode simulation, which is based on Tsuprem4/Medici. And the circuit level simulation will be carried out on the Candence platform.

Optimized latch-up design of a high voltage nLDMOSFET

Abstract: Both drain-side and source-side engineering by adding N ad and P ad layers to obtain a weak snapback characteristic nLDMOS are presented in this work. It is a novel method to reduce trigger voltage (V t1 ) and to increase holding voltage (V h ). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage and holding voltage distributions of these novel HV nLDMOS devices.

A study of p stopper effect on 30V-gate/80V-dram bi-directional NMOSFET and 80V ESD protection BJT

Abstract: This paper describes the impact of the introduction of a p stopper to a 30V-gate bi-directional NMOSFET and an ESD protection BJT fabricated using our 80V-class HV-MOS process. We found that the p stopper that selectively formed below the channel region of the NMOSFET not only helped to prevent the S-D punch-through but also caused some important effects: (i) alleviated the electric field crowding without sacrificing the optimized resurf breakdown voltages at high drain bias, and (ii) intensified the crowding near the channel surface with increasing the channel length at a high common-G/S/D bias. We confirmed that the former effect improved both the current and the on/off-breakdown performance while the latter did not decrease the usable source bias, which equals the rated gate voltage of 30V. The p stopper applied to the core base edge of the BJT also made some snapback current evade from flowing near the surface, which increased the secondary breakdown current by over 30%. These p stoppers did not require an extra mask step in our 80V-MOS process.

Thermo-sensitive snapback behavioral model intended for electro-thermal simulation of power MOSFETs

Abstract: It is known that a second breakdown phenomenon similar to that observed in bipolar transistors can occur in power VDMOS, resulting from drain current snapback. A model for the drain current snapback phenomenon and its temperature dependence were investigated up to 300°C involving the avalanche multiplication of the channel current and the activation of the parasitic bipolar transistor. After presenting the theory, this model is compared with TLP (Transmission Line Pulsing) experimental results. Good agreement is achieved between calculated and measured boundaries of the current before and after the snapback has occurred.