Showing papers on "Snapback published in 2011"

Output Stage of a Power Amplifier Having a Switched-Bulk Biasing and Adaptive Biasing

Abstract: A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

Voltage Snapback in Amorphous-GST Memory Devices: Transport Model and Validation

Abstract: Charge transport in amorphous chalcogenide-GST used for memory devices is modeled using two contributions: hopping of trapped electrons and motion of band electrons in extended states. The type of feedback that produces the snapback phenomenon is described as a filamentation in energy that is controlled by electron-electron interactions between trapped electrons and band electrons. The model thus derived is implemented within a state-of-the-art simulator. An analytical version of the model is also derived and is useful for discussing the snapback behavior and the scaling properties of the device.

Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self-Heating

Abstract: A physics-based compact model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors including impact ionization, subsequent snapback (SB), and self-heating (SH) is presented. It is observed that the SB effect is caused by the turn-on of the associated parasitic bipolar transistor. The model includes the effect of device SH using resistive thermal networks for each region. Comparisons of modeling results with device simulation data show that, over a wide range of bias voltages, the model exhibits excellent accuracy without any convergence problem.

Apparatuses, devices and methods for sensing a snapback event in a circuit

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar

Abstract: A second-breakdown phenomenon (It2) in a drain-extended n-type metal-oxide-semiconductor (DENMOS) is associated with complex triggering of a parasitic bipolar transistor. Full comprehension of the problem requires 3-D modeling; however, there is even deficiency in the understanding of the phenomenon occurring in the 2-D cross-sectional plane. We present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a DENMOS device. We present a detailed analysis of the current paths involved during the bipolar turn-on. We show that a strong snapback is triggered due to coupling of the parasitic bipolar turn-on in a deeper region of the p-body and avalanche injection at the drain junction. Furthermore, we show that the ballast resistor formed in the drain region due to current crowding of electrons under high-current conditions can be modeled through a simplified 1-D analysis of the n+/n- resistive structure.

High-voltage ESD protection device

Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

A convergence robust method to model snapback for ESD simulation

Abstract: A new behavior modeling method is presented to model ESD protection devices with voltage snapback. It resolves the convergence problem induced by snapback characteristic. The model can pass HBM, MM and TLP transient simulations in SPICE. The reason for convergence robustness is also discussed.

Nanosecond transient thermoreflectance imaging of snapback in semiconductor controlled rectifiers

Abstract: Transient thermoreflectance imaging method has been applied for the first time to reveal current distribution in ESD protection devices through the surface temperature change due to self heating. Experimentally calibrated temperature images are obtained of a multiple finger, 80 square micron 100V NLDMOS-SCR device in snapback operation regimes for different current levels (1.15–1.47A) and at different times ranging between 100 nanoseconds to one millisecond after the ESD pulse. The novel applied methodology demonstrates a practical and straightforward way to characterize non-uniform temperature and current distribution in ESD structures, revealing effects of non-simultaneous triggering of individual fingers on the multiple finger SCR device.

Design of ESD protection device using body floating technique in 65 nm CMOS process

Abstract: A floating body electrostatic discharge (ESD) protection circuit positioned between and coupled to an I/O pad and an internal circuit is presented. A small NMOS transistor is used to control the body of a main NMOS transistor. When the small NMOS transistor is triggered, the body of the main NMOS transistor remains grounded. If the small NMOS transistor has not been triggered, the body of the main NMOS transistor remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. The proposed ESD protection circuit is designed in 65 nm CMOS technology.

A novel double-trench LVTSCR used in the ESD protection of a RFIC

Abstract: A low-voltage triggering silicon-controlled rectifier (LVTSCR), for its high efficiency and low parasitic parameters, has many advantages in ESD protection, especially in ultra-deep sub-micron (UDSM) IC and high frequency applications. In this paper, the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail. These parameters include anode series resistance, gate voltage, structure and size of devices. In addition, a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment. Also, its snapback characteristics can obey the ESD design window rule very well. The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

Abstract: The modified ESD protection structure with N-well implant in the drain region has been proposed and investigated in this paper. Table I lists the comparison of TLP, HBM/MM ESD robustness, and TLU immunity between HV GGNMOS structure with and without N-well implant. By the influence of N-well implant, many drawbacks such as double snapback, soft leakage degradation, non-uniform current conduction, low ESD robustness, and weak TLU immunity in the common HV GGNMOS device are overcome efficaciously. Without additional mask or process cost, the proposed ESD device with low trigger voltage and high holding voltage is effectively employed for power clamp protection in HV CMOS ICs without latchup or transient-induced latchup damage.

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

Abstract: This paper presents the device-level electrostatic discharge (ESD) robustness improvement for integrated vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate-voltage dependence of the second breakdown current (It2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

ESD Engineering Fully Silicided Large MOSFET Driver for Maximum $It\hbox{1}$ Performance

Abstract: Simultaneous optimization of LDD and antipunch-through implant conditions for ESD performance of very large width silicided output driver NMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulsewidth, are detailed.

Esd protection circuit of semiconductor integrated circuit and esd protection element thereof

Abstract: PROBLEM TO BE SOLVED: To control the holding voltage Vh to a proper voltage equal to or higher than the power supply voltage without causing significant decrease of the protection capability by suppressing increase in the layout area when compared with a conventional structure.SOLUTION: The ESD protection element 21 includes an SCR element as a snapback characteristic element having the snapback characteristics, and a diode 13 connected with the SCR element as a voltage addition element for adding the snapback start voltage Vt1 by an amount of the element voltage and bringing the hold voltage Vh twice as high as the element voltage. The hold voltage Vh is adjusted between the power supply voltage Vcc and the withstand voltage of a protected element by adjusting the element voltage of the diode 13.

Origin of It2 drop depending on process and layout with fully silicided ggMOS

Abstract: Source-drain process optimization and a diffusion layout technique enable reduction of the snapback voltage (Vt1). Lowering Vt1 of the fully silicided ggMOS enabled low on-resistance and a higher failure current (It2) combined stably in multi-finger turn-on operation. Moreover, to meet both hot-carrier reliability and the ESD requirement, lightly doped drain (LDD) process was obtained.

Double snapback effect in LDMOS based on non-isothermal simulation

Abstract: This paper reports a novel effect in Lateral Diffused MOS (LDMOS) transistors—double snapback effect. Based on non-isothermal simulation, we find the IV characteristic of LDMOS exhibits twice snapbacks phenomenon. TCAD tools are employed to investigate the physical mechanism of the double snapback phenomenon. The results show that the first snapback is a electrical snapback, while the second snapback is a thermal snapback. In more detail, the first snapback is induced by turn-on of the parasitic bipolar transistor activated by hole current density due to the avalanche ionization. The second snapback is originated from the thermal run-away due to the significant increase of the drain junction temperature.

Modeling the 3D self ballasting behavior and filamentation under high current stressing in DeNMOS

Abstract: A critical understanding of self ballasting behavior due to current crowding of avalanche generated carriers in a DeNMOS is developed. Then we study its performance under the gate biased conditions. The impact of flow of holes and electron in the bulk and across the surface — on the snapback-back features has been critically evaluated through variations in the device structure (associated with process parameter) which has also been extensively studied through 2D & 3D TCAD simulations. We demonstrate that after an initial homogeneous triggering (due to bipolar snapback), self heating preferentially activates the 2D array of bipolars in the bulk and subsequently current instability under negative resistance regime (as the bipolar turns on) leads to inhomogeneous triggering in the 3D.

Snapback capable NLDMOS, DMOS and extended voltage NMOS devices

Abstract: In an NLDMOS, DMOS and NMOS device, the ability is provided for withstanding snapback conditions by providing one or more p+ emitter regions interdigitated between drain regions having drain contacts and electrically connecting the drain contacts to contacts of the emitter regions.

Bond pad with integrated transient overvoltage protection

Abstract: A method of forming an over-voltage clamp structure and overvoltage clamp structure is provided. In some embodiments, the overvoltage clamp structure includes a substrate (708) and a bond pad (700) disposed over the substrate, planar high voltage MOS devices formed in the substrate beneath the bond pad (100c) including the door. A high voltage MOS device (100c) includes a well formed in the substrate (100,115), and doped shallow region formed in the well (130,135,140,145) is disposed over the well It may include a gate (160). In some embodiments, the clamp structure showed no leakage of soft faults after the first snapback, while significantly reducing the device area, greatly extend the ESD robustness.

Characterization analysis of UDSM LVTSCR under TLP stress

Abstract: The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.

ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR

Abstract: Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis. According to this criterion, three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that, as the second snapback voltage decreased from 25.4 to 8.1 V, the discharge ability of the optimized structure increased from 0.57 to 3.1 A.

Vertical gate RF SOI LIGBT for SPICs with significantly improved latch-up immunity

Abstract: Based on the previous achievements in improving latch-up immunity of SOI LIGBT, process simulation on our proposed VG RF SOI NLIGBT was carried out with TCAD to provide a virtually fabricated device structure. Then, an approximate latching current model was derived according to the condition of minimum regenerative feedback couple between the parasitic dualtransistors. The model indicates that its latching current is a few orders higher than those before. Further verification through device simulation was done with TCAD, which proved that its weak snapback voltage in the off state is about 0.5-2.75 times higher than those breakdown voltages reported before, its breakdown voltage in the off state is about 19V higher than its weak snapback voltage, and its latching current density in the on state is about 2-3 orders of magnitude higher than those reported before at room temperature due to hole current bypass through P+ contact in P-well region. Therefore, it is characterized by significantly improved latch-up immunity.

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35µm Bipolar-CMOS-DMOS Process

Abstract: A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 μm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.