Showing papers on "Snapback published in 2013"

Extended drain non-planar mosfets for electrostatic discharge (esd) protection

Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

Abstract: For high-voltage output driver, the lateral DMOS (LDMOS) is often used for both output function operation and self-protection against electrostatic discharge (ESD) events. In this work, a new structure of LDMOS output device with embedded SCR has been proposed and verified in a 0.25-μm 60-V BCD process. This new structure, with additional p+ and n+ implantation regions added between the drain contact and poly-gate of LDMOS, can keep it stably in the high-current holding region after snapback. By using this structure, the LDMOS can provide high enough self-protected ESD robustness for applications in the high-voltage output drivers.

A novel snapback-free reverse conducting IGBT with anti-parallel Shockley diode

Abstract: A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with anti-parallel Shockley diode is proposed. By introducing an additional isolated p-n junction at the anode, the effect of anode-short is eliminated, and accordingly, the snapback problem is solved in the novel RC-IGBT. The snapback-free characteristics can be realized in a single cell with a width of less than 10 μm. Besides, the conduction voltages are significantly reduced and the distributions of minority carrier and of current are more uniform than the conventional RC-IGBT, in both the forward and the reverse conduction states. The tradeoff between Eoff and Von in the forward operation case and the tradeoff between Qrr and Von in the reverse operation case are both optimized in this paper.

A high reliable reverse-conducting IGBT with a floating P-plug

Abstract: A current distribution model is presented for the RC-IGBTs both at IGBT mode and DIODE mode. According to the analytical model, smaller cell size would be better for the distribution of the current density and full utilization of the silicon, but the snapback would be worse. Then a novel RC-IGBT with a floating P-plug is proposed and investigated by simulations. The results show that it can suppress the snapback phenomena effectively. More importantly, the silicon utilization ratio is much higher than the others RC-IGBTs and the current is uniformly distributed in the whole wafer both at IGBT mode and DIODE mode that ensured the high temperature reliability of the RC-IGBT.

Reverse conducting type insulated gate bipolar transistor without snapback effect

Abstract: A reverse conducting type insulated gate bipolar transistor without a snapback effect belongs to the technical field of semiconductor power devices. A P floating region (7) is introduced between an N collector region (9) and an N buffer region (8) of a conventional RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) so that the snapback effect of the reverse conducting type insulated gate bipolar transistor is eliminated, and the turn-off loss of the devices is reduced. The novel structure reduces the cellular length and the effective area of the N collector region (9) and increases the short-circuit resistance of a collector, the transmission efficiency of the P floating region (7) is higher than that of a P collector region (10), and the resistance of an N-drift region (6) is reduced through a conductance modulation effect, so that the snapback effect is eliminated. When the reverse conducting type insulated gate bipolar transistor reversely works, a parasitic transistor formed by the N-drift region (6), the P floating region (7) and the N collector region (9) is opened, so that a current path is provided, so as to form positive feedback of a PNPN (Positive-Negative-Positive-Negative) four-layer structure with the a P body region (5), the on-resistance when each device is reversely conducted is reduced, and the relatively low on-state voltage and the rapid shutdown are realized.

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Abstract: High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

Abstract: The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

Reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P floating layer current bolt

Abstract: The invention discloses a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with a P floating layer current bolt, and belongs to the field of semiconductor power elements. A medium buried layer is led in between an N collector region and a P collector region of a traditional RC-IGBT, and the P floating layer current bolt is led into an N-type buffering layer above the medium buried layer. According to the RC-IGBT with the P floating layer current bolt, other parameters of an element are not affected, break-over voltage of a snapback is obviously lowered, a reverse recovery soft factor is improved, current is distributed uniformly, local over-heating phenomenon is avoided, and the reliability of the RC-IGBT is improved.

Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

Abstract: Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102 dc switching cycles.

Rf ldmos device and fabrication method thereof

Abstract: A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed which additionally includes a lightly-doped P-type buried layer under a P-type channel region and a moderately-dope P-type buried layer in the lightly-doped P-type buried layer. The two buried layers result in a lower base resistance for an equivalent parasitic NPN transistor, thereby impeding the occurrence of snapback in the device. Additionally, an equivalent reverse-biased diode formed between the channel region and the buried layers is capable of clamping the drain-source voltage of the device and sinking redundant currents to a substrate thereof. Furthermore, the design of a gate oxide layer of the RF LDMOS device to have a greater thickness at a proximal end to a drain region can help to reduce the hot-carrier effect, and having a smaller thickness at a proximal end to the source region can improve the transconductance of the RF LDMOS device.

Electrostatic discharge protection device structures and methods of manufacture

Abstract: An ESD protection device comprising an SCR -type circuit (300) including a PNP transistor (101) and NPN transistor (106) incorporates a Zener diode (108) which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area (308) of an N-type well (307). One or more diodes (105) connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers (314a, 314b) between doped regions (310, 313, 315) instead of gate oxide technology significantly reduces unwanted leakage currents.

Verification of Snapback Model by Transient $I$ – $V$ Measurement for Circuit Simulation of ESD Response

Abstract: It is demonstrated that if the compact model of a snapback-type device is calibrated using only pulsed I-V data, it may not correctly reproduce the device response to arbitrary electrostatic discharge (ESD) waveforms. Transient I-V measurements are demonstrated to improve the completeness of the device characterization and model verification. Given an accurately calibrated ESD compact model, circuit simulations may be used to identify device-tester interactions that have been reported to cause unexpected damage during ESD testing. The interaction between a snapback device and an ESD tester can be understood in the context of a relaxation oscillator.

Method and apparatus to improve ESD robustness of power clamps

Abstract: A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.

Reliability Design of Source/Drain Adaptive Layers in an HV Power nLDMOS

Abstract: Reliability issues are very important especially for the high-voltage (HV) devices. Unfortunately, an HV nLDMOS is often damaged by a latch-up (LU) problem when it triggered by a transient noise and a bias condition VDDmax is greater than that of the device holding-voltage (Vh). The snapback phenomena of the new adding adaptive layers in the source/drain ends of an nLDMOS are investigated in this paper. It is a novel method to reduce the surface field, control the trigger voltage and holding voltage. Experimentally, the right-shifting characteristic of snapback I-V curves depends on new adding Pad, LPad, Nad, and LNad parameters, respectively. Eventually, these source/drain adaptive layers of an nLDMOS can effectively improve the LU immunity under an HV operation.

Evaluation of ESD/LU Reliabilities by Different SCR Layout Types in a 0.35μm 3.3V CMOS Process

Abstract: This paper aimed at the evaluation of layout dependence on ESD/LU reliabilities in the 0.35μm 3.3V low-voltage triggered silicon-controlled-rectifier (LVTSCR) DUTs. In this work, the parameter of channel L in a pMOS and the parameter S of an SCR are varied to study the influence on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2), respectively. Eventually, it can be found that the layout illustration of type-2 has a higher It2 than that of type-1, i.e., the ratio of (It2)type-2/(It2)type-1 > 3 among all the LVTpSCRs. Meanwhile, the holding voltage of all SCR devices are latch-up free while operated at 3.3V. Therefore, the type-2 layouts of SCR devices are so excellent structure in the ESD/LU reliability considerations for this 0.35μm 3.3V CMOS process.

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Abstract: An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process

Abstract: An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Abstract: In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

Layout strategy of P + pick-up on the LV nMOST ESD reliability for 0.6μm to 0.18μm CMOS technologies

Abstract: A multi-finger LV nMOST is often applied to the input/output pads as electrostatic discharge protection (ESD) elements. However, the non-uniform turned-on phenomenon always occurred, i.e. these sub-nMOSTs can't be turned-on simultaneously. The ESD current will be passed through a few turned-on MOSTs. It was due to the R B resistance of parasitic bipolar transistor for each finger transistor in silicon bulk region is quite different. In this paper, the P+ pick-up area in source-side influence on the protection components in ESD capability of input/output pads will be investigated for 0.6μm to 0.18μm CMOS technologies. Here, the best stripe number choice of P+ pick-up will be carried out the important snapback parameters. We focus on exploring the value of secondary breakdown current (I t2 ) and some physical parameters for the ESD robustness. Hopefully, it does effectively enhance ESD capability to solve the exactly non-uniform turned-on issue.

Enhanced PMOS-triggered PMLSCR with robust EOS immunity

Abstract: An enhanced PMOS-triggered PMLSCR is proposed. Under the condition that both PNP and NPN BJT's are triggered simultaneously, voltage overshoot and turn-on uniformity can be further improved. From TCAD simulation, it is clear that with the help of trigger current, conduction path of SCR goes deeper and snapback voltage is reduced. By the designed power sequence, holding voltage and current of SCR devices considering self-heating effect are attained. Robust EOS immunity can be assured accordingly.

Impact of Drain-Side nWell Engineering on ESD Robustness in 0.35μm LV MOSTs

Abstract: A multi-finger nMOST is widely used as an electrostatic discharge (ESD) protection device especially in the input/output pads. However, the contact-spiking leakage phenomenon in an MOST are seriously impacted the ESD capability. Therefore, one drain-side engineering is investigated in this paper, i.e., by adding a negative-type well (nWell) structure in the drain-side of device, hoping to avoid contact-spiking issues to enhance ESD reliability. The nWell width variations will be explored the influence on snapback parameters of ESD devices in a 0.35μm 3.3V low voltage (LV) process. However, after a systematic analysis, it is found that adding an nWell structure in the drain-side will lower ESD capability (It2 value) about 24% for this process. And, as compared with the original reference DUT, adding any nWell in the drain-side will make the Vh value slightly decreasing about 1%.

Study of graphene field-effect transistors under electrostatic discharge stresses

Abstract: Graphene field-effect transistors (GFETs) are characterised for the first time under electrostatic discharge stresses. The GFETs are measured from the transmission line pulsing (TLP) tester and very fast TLP (VFTLP) tester. The turn-on behaviour influenced by back gate voltage is investigated. The I-V curve of the GFETs shows no characteristic of snapback from TLP or VFTLP measurement.