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Showing papers on "Snapback published in 2017"


Journal ArticleDOI
TL;DR: In this paper, the authors presented the drift region SuperJunction pillars placed at the anode side of the structure rather than the cathode side for the purpose of simplifying the fabrication requirements.
Abstract: In this letter, we present the “anode-side” SuperJunction trench field stop+ IGBT concept with drift region SuperJunction pillars placed at the anode side of the structure rather than the cathode side. The extent of the pillars toward the cathode side is shown to pose a tradeoff between fabrication technology capabilities (and cost) versus the device performance, by extensive TCAD simulations. The proposed device structure simplifies the fabrication requirements by steering clear from the need to align the cathode side features with the SuperJunction pillars. It also provides an extra degree of freedom by decoupling the cathode design from the SuperJunction structure. Additionally, the presence of SuperJunction technology in the drift region of the “anode-side” SJ Trench FS+ IGBT results in 20% reduction of ON-state losses for the same switching energy losses or, up to 30% switching losses reduction for the same ON-state voltage drop, compared with a 1.2-kV breakdown rated conventional FS+ Trench IGBT device. The proposed structure also finds applications in reverse conducting IGBTs, where a reduced snapback can be achieved, and in MOS-controlled thyristor devices.

33 citations


Journal ArticleDOI
TL;DR: In this article, a hybrid unipolar/bipolar operation with a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region.
Abstract: In this paper, ultrahigh-voltage (UHV) SiC devices with hybrid unipolar/bipolar operation are introduced and demonstrated. As the first step of such a device, a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region. A “snapback” phenomenon is intensively investigated by analytical modeling, device simulation, and experiment and a design guideline of snapback-free hybrid operating MPS diodes is presented. Using the design guideline, snapback-free MPS diodes are fabricated and forward characteristics are investigated. By using a proper edge termination structure, a UHV SiC MPS diode with breakdown voltage of 11.3 kV is demonstrated.

32 citations


Journal ArticleDOI
TL;DR: In this article, a reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation.
Abstract: A novel 500 V reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation. The RC is realized by the internal diode, which consists of two p-i-n diodes (D1 and D2). The two diodes are connected in series. In the RC-state, the current flows through D1 first and then through D2. D2 is embedded in the anode region of the proposed DED-LIGBT and is fully isolated by the deep-oxide trench. In the forward conducting state, D2 is reverse biased and the electrons from the N+ cathode can only flow into the P+ anode. The DEDs reroute the electron current path, and thus, the snapback is avoided. Moreover, by adjusting the width of D2 ( ${W}_{b})$ , the internal diode of the DED structure achieves superior reverse recovery time ( ${t}_{\text {rr}})$ and reverse recovery peak current ( ${I}_{\text {rrm}})$ to the conventional SOI p-i-n diode.

20 citations


Proceedings ArticleDOI
01 May 2017
TL;DR: In this paper, a 600V SOI shorted-anode LIGBT with multi-segment anode (MSA) is proposed and investigated and a compact analytical model is further presented to evaluate the impact of key parameters of the MSA on the snapback voltage (V sb ).
Abstract: A new 600V SOI shorted-anode LIGBT with multi-segment anode (MSA) is proposed and investigated in this paper. The device features a multi-segmented P+ anode and p-buried layers (PBL) formed in both anode and cathode regions. The combination of MSA and the PBL below the anode increase the anode distributed resistance (R sa ) and effectively suppress snapback effect with small dimensions in both x- and z-directions. The PBL below cathode n+ serves as a low-resistance bypass for on-state hole current and is conducive to latch-up immunity. A compact analytical model is further presented to evaluate the impact of key parameters of the MSA on the snapback voltage (V sb ). Simulation shows that the MSA LIGBT achieves the V sb off ), the MSA LIGBT reduces the on-state voltage (F on ) by 50% compared to the separated shorted anode (SSA) LIGBT. The MSA LIGBT exhibits no latch-up issue at the high voltage and high current up to 1600A/cm2. The short circuit withstand time of the proposed structure achieves 6X improvement compared to that of the conventional LIGBT.

20 citations


Journal ArticleDOI
TL;DR: In this paper, the authors presented the electrostatic discharge (ESD) behavior of grounded gate tunnel FET (ggTFET) with detailed physical insight into the device operation, 3-D filamentation and failure under ESD stress conditions.
Abstract: For the first time, we present the electrostatic discharge (ESD) behavior of grounded gate tunnel FET (ggTFET) with detailed physical insight into the device operation, 3-D filamentation and failure under ESD stress conditions. Current as well as time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the unique failure mechanism is studied using both 2-D and 3-D technology computer aided design simulations. The interaction between the band-to-band tunneling, avalanche multiplication, and thermal carrier generation leading to voltage snapback and failure is presented in detail. In addition, electro-thermal instability initiated filamentation and snapback discovered in the ggTFET is explained. The impact of various technology and device design parameters on the ESD behavior and robustness of TFETs is discussed. This has helped developing guidelines to design ESD robust TFETs for efficient protection concepts. Finally, the charge device model behavior of ggTFET device is discussed.

20 citations


Proceedings ArticleDOI
01 May 2017
TL;DR: In this paper, a 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time.
Abstract: A 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time. The AB RC-IGBT features a buffer layer with alternately doped N+ and P regions. The AB is separated from the collector by a part of N-drift region. The P buffer serves as the electron barrier during the unipolar mode and forces the electrons to flow through the high-resistance N-drift region between the buffer and the collector. Consequently, the snapback is suppressed with a fairly small cell pitch of 30μm. In the blocking state, the P buffer is fully depleted while the N+ buffer is not fully depleted yet. Therefore, the electric field terminates in the buffer layer and a high BV is ensured. The turn-off loss of the proposed AB RC-IGBT is reduced by 20% compared with that of the conventional RC-IGBT for the same forward on-state voltage drop.

19 citations


Journal ArticleDOI
TL;DR: In this article, a snapback-free fast-switching lateral insulated-gate bipolar transistor (LIGBT) with low power loss and high ruggedness is proposed and investigated by simulation.
Abstract: A snapback-free fast-switching lateral insulated-gate bipolar transistor (LIGBT) with low power loss and high ruggedness is proposed and investigated by simulation. The proposed device features a polysilicon regulative resistance (PR) and a trench cathode (TC), named PRTC LIGBT. The PR is employed to not only suppress the snapback effect by regulating the voltage drop between P+ anode and N-buffer, but also improve the tradeoff between the on-state voltage drop ( $\text{V}_{ \mathrm{\scriptscriptstyle ON}})$ and turn-off loss ( $\text{E}_{ \mathrm{\scriptscriptstyle OFF}})$ . The TC widens the hole current path and decreases the distributed resistance under N+ cathode, and thus delivers a high latch-up ruggedness. Additionally, the PRTC LIGBT exhibits a blocking characteristic irrelevant to P+ anode concentration (NA), like a p-i-n diode (P-well, N-drift, and N-buffer), owing to its undepleted N-buffer region. Simulation results show that the PRTC LIGBT eliminates the snapback and reduces the $\text{E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 28% compared to the segmented trenches in the anode (STA) region LIGBT. Its short-circuit time is prolonged by 53% and 40% compared to those of the STA LIGBT and PR LIGBT (without TC), respectively.

19 citations


Journal ArticleDOI
TL;DR: In this paper, a modified power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device, which can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.
Abstract: Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.

18 citations


Journal ArticleDOI
TL;DR: In this paper, a resistor-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances.
Abstract: Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.

18 citations


Proceedings ArticleDOI
01 May 2017
TL;DR: In this article, a self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented, where a parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDM OS to operate within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown.
Abstract: A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.

10 citations


25 Sep 2017
TL;DR: In this article, the authors used the Deutsche Bundesbank for the data used in the studies reported here, and they were grateful to Claudio Borio, Stijn Claessens, Dietrich Domanski, Peter Ho rdahl, Krista Hughes, Ilhyock Shim, Vladyslav Sushko, Kostas Tsatsaronis and Dora Xia for excellent research assistance.
Abstract: 1 I am grateful to Claudio Borio, Stijn Claessens, Dietrich Domanski, Peter Ho rdahl, Krista Hughes, Ilhyock Shim, Vladyslav Sushko, Kostas Tsatsaronis and Dora Xia for comments and to Jose Marí a Vidal Pastor for excellent research assistance. I thank the Deutsche Bundesbank for the data used in the studies reported here. The views expressed here are my own and do not necessarily reflect those of the BIS.

Patent
12 Dec 2017
TL;DR: In this article, a superjunction reverse conducting-insulated gate bipolar transistor (IGBT) with a collector groove was introduced, and the collector structure has an effect equivalent to a buffer layer.
Abstract: The invention belongs to the technical field of a power semiconductor, and particularly relates to a superjunction reverse conducting-insulated gate bipolar transistor (IGBT) with a collector groove. Compared with a traditional superjunction RC-IGBT structure, the superjunction RC-IGBT has the advantages that a collector groove structure is mainly introduced to a bottom current collection region, an N drift region at the bottom of the collector groove can be consumed by P-type strips when a new device is positively conducted and does not enter a bipolar mode, so that an electron current path is occupied, the effective electron concentration is reduced, the electron current distribution resistance around the current collection region is increased, and a snapback effect of the device can be eliminated by the new device under relatively small cell size; and when the new device is switched off, the collector structure has an effect equivalent to a buffer layer, and the device can be enabled to bear high pressure. The superjunction RC-IGBT has the beneficial effects that compared with the traditional superjunction RC-IGBT structure, the snapback effect can be eliminated under smaller cell size, meanwhile, the superjunction RC-IGBT has faster switch-off speed, and the current distribution is more uniform in a reverse diode mode.

Proceedings ArticleDOI
01 Jan 2017
TL;DR: Post failure analysis reveals role of inverse piezoelectric effect, fringing electric field, contact resistivity, temperature and field induced contact metal migration in degradation of AlGaN/GaN HEMTs under ESD conditions.
Abstract: This experimental study reports ESD failure analysis of AlGaN/GaN HEMTs. Effect of MESA isolation, gate and parasitic MESA Schottky diode on ESD robustness is studied. Cause of snapback instability, multiple NDCs and transition from soft-to-hard failure are discussed. Unique leakage trends and cumulative nature of degradation are discovered. Post failure analysis reveals role of inverse piezoelectric effect, fringing electric field, contact resistivity, temperature and field induced contact metal migration in degradation of AlGaN/GaN HEMTs under ESD conditions.

Journal ArticleDOI
TL;DR: In this article, a novel silicon controlled rectifier (SCR) with high holding voltage for electrostatic discharge (ESD) protection is proposed and investigated and an optimized 7.4 V with a maximum failure current of 14.7 mA/ is obtained by the simulation.
Abstract: A novel silicon controlled rectifier (SCR) with high holding voltage ( for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (, the two SCRs are turned on at the same time to induce the first snapback with high (. As the increases, the SCR2 will be turned off because of its low current gain. Therefore, the will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high (. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized of 7.4 V with a maximum failure current ( of 14.7 mA/ is obtained by the simulation.

Proceedings ArticleDOI
20 Jun 2017
TL;DR: In this paper, the authors attempted to measure the two-port S-parameters of an ESD protection device using a vector network analyzer, bias tee, direct current power supply, and electronic load.
Abstract: The operating characteristics and protection against electrostatic discharge (ESD) offered by a protection device when implemented in a real circuit may differ from those suggested via a circuit simulation, particularly at the system level. We assumed that this can be partly attributed to the failure of the snapback characteristics to account for the frequency responses of the pass and reflection characteristics of the device. In this study, we attempted to measure the two-port S-parameters of an ESD protection device using a vector network analyzer, bias tee, direct current power supply, and electronic load. We also proposed a circuit configuration for a radio frequency simulator that is able to model the frequency response of an ESD protection device for system-level ESD stress simulation. To evaluate the proposed method, we compared the simulated ESD stress voltage waveform with that actually measured when ESD was applied to a transient voltage suppressor diode.

Proceedings ArticleDOI
01 Sep 2017
TL;DR: In this paper, the authors describe the development of empirical simulation models for snapback-based cascode nmos ESD transistors and demonstrate the use of empirical models for quantitative optimization of ESD protection.
Abstract: This work describes the development of empirical simulation models for snapback-based cascode nmos ESD transistors. Behavioral language VerilogA code was used to combine regular SPICE model with TLP characteristics, at triggering voltage dependent on two gate voltages. The use of empirical models for quantitative optimization of ESD protection was demonstrated on schemes and Si.

Patent
04 Jan 2017
TL;DR: In this paper, the authors proposed a high-speed SOI-LIGBT (Lateral Insulated Gate Bipolar Transistor) for power semiconductors, where an N+ current collection region is introduced to a part near to a P+ current collector region of a new device, and when the new device is switched off, the N+ collection region and the poly-silicon resistance region provide a discharge passage for electrons stored in a drift region, and the switch-off speed of the new devices is increased.
Abstract: The invention belongs to the technical field of a power semiconductor, and in particular relates to a high-speed SOI-LIGBT (Lateral Insulated Gate Bipolar Transistor). Compared with a traditional LIGBT, an N+ current collection region is introduced to a part near to a P+ current collection region of a new device, and the N+ current collection region is connected with a current collector by a poly-silicon resistance region; and when the new device is switched off, the N+ current collection region and the poly-silicon resistance region provide a discharge passage for electrons stored in a drift region, and the switch-off speed of the new device is increased. Compared with a traditional short-circuit positive electrode LIGBT, a voltage required for diode conduction of the P+ current collection region/N buffer region is mainly dependent on voltage drop of the poly-silicon resistance region, the device can be controlled to enter a bipolar mode by reducing the doping concentration or the size of the poly-silicon resistance region, and a Snapback effect is effectively suppressed. Compared with the traditional LIGBT, the high-speed SOI-LIGBT has beneficial effects that the high-speed SOI-LIGBT has excellent performance of high speed and low switch-off loss; and compared with the traditional short-circuit positive electrode LIGBT, the high-speed SOIL-LIGBT has the advantages that a poly-silicon resistor liable to integrate is used for suppressing the Snapback effect, the process is simple and practicable, and the device parameter is simple and flexible to design.

Journal ArticleDOI
Jia Qiang Xie, Li Ma, Wei Li, Yong Gao, Ning Mei Yu 
TL;DR: Three novel ways to alleviate the reverse conducting insulated gate bipolar transistor (RC-IGBT) snapback phenomenon are proposed by introducing the floating field stop layer with a lightly doped p-floating layer and recess structure at the backside, which would not degrade the blocking capability but can suppress thesnapback phenomenon effectively.
Abstract: We propose two novel ways to alleviate the reverse conducting insulated gate bipolar transistor (RC-IGBT) snapback phenomenon by introducing the floating field stop layer with a lightly doped p-floating layer and recess structure at the backside. The floating field stop layer is submerged in the N-drift region and located several micrometers above the P+ anode region, which would not degrade the blocking capability but can suppress the snapback phenomenon effectively. When the collector length exceeds 100 μm, the snapback voltage ΔVSB of the floating field stop RCIGBTwith the p-floating layer can be less than 0.5V. Furthermore, the recess structure at the backside can separate the N+ short and P+ anode region, which will be beneficial to eliminate the snapback. Finally, an RC-IGBTwith a floating buffer layer and recess at the backside is proposed. Compared to the RC-IGBT featuring an oxide trench between the N+ short and P+ anode, the proposed one has utilized the simple recess structure to replace the costly oxide trench and achieved the identical characteristics simultaneously.

Proceedings ArticleDOI
01 Dec 2017
TL;DR: In this paper, an improved silicon-controlled rectifier (DSCR) with higher holding voltage and smaller area is proposed and fabricated in a 05 μΜ HV CDMOS process.
Abstract: Silicon-Controlled Rectifier (SCR) is well known for its good robustness, but its deep Snapback makes it have a low holding voltage, it will bring a latch-up issue An improving silicon-controlled rectifier (DSCR) device with higher holding voltage and smaller area is proposed and fabricated in a 05 μΜ HV CDMOS process The 3D simulation results show that the DSCR has same working mechanism with SCR, and enlarging the D1 and D2 is effective to increase DSCR's holding voltage TLP test results show that enlarging D1 and D2 to 8 μm makes the DSCR's holding voltage from 24 V to 795 V without increasing layout area

Proceedings ArticleDOI
01 Sep 2017
TL;DR: In this article, a detailed physical insight into the ESD behavior and unique failure mechanisms of Pentacene Organic Thin Film Transistors (OTFTs) is reported, and the influence of channel field and Surface Assembled Monolayer (SAM) on the carrier transport and failure threshold is addressed.
Abstract: Detailed physical insight into the ESD behavior and unique failure mechanisms of Pentacene Organic Thin Film Transistors (OTFTs) is reported. Orders of magnitude difference in channel current under ESD time scales, when compared to DC time scales, is discovered. Moreover, unique three stage TLP characteristics with snapback state and novel failure mechanism are reported. Finally, influence of channel field and Surface Assembled Monolayer (SAM) on the carrier transport and failure threshold is addressed.

Journal ArticleDOI
TL;DR: In this paper, the robustness of GaN power field effect transistors, including the vertical UMOSFET, vertical DMOS-FET and lateral p-AlGaN gate HEMT, was investigated by analyzing their safe operating areas (SOA) using finite-element analysis device simulation.
Abstract: Robustness of GaN power field-effect transistors, including the vertical UMOSFET, vertical DMOSFET, and lateral p-AlGaN gate HEMT is studied by analyzing their safe operating areas (SOA) using finite-element-analysis device simulation. At off-state gate voltages, the devices are forced into high-voltage, high-current avalanche breakdown. Assuming isothermal conditions at 300 K, the simulated DMOSFET SOA exhibits high robustness, while the UMOSFET and the p-AlGaN gate HEMT experiences current snapback. The simulated robustness of both the DMOSFET and the UMOSFET degrades when realistic temperature dependence is included in the non-isothermal case, with current filamentation in high dissipation areas, leading to a more pronounced current snapback.

Patent
20 Jun 2017
TL;DR: In this paper, a low-resistance silicon on insulator-lateral insulated gate bipolar transistor (SOI-LIGBT) device capable of preventing a snapback effect and a manufacturing method thereof was provided.
Abstract: The invention provides a low-resistance silicon on insulator-lateral insulated gate bipolar transistor (SOI-LIGBT) device capable of preventing a snapback effect and a manufacturing method thereof. A cell structure of the low-resistance SOI-LIGBT comprises a substrate, a buried oxide layer, a thick dielectric layer, a thick silicon layer drift region, a P well region, a P-type heavily-doped emitter region, a first N-type heavily-doped region, an N-type buffer region, a P-type heavily-doped collector region, a second N-type heavily-doped region, a collector dielectric blocking layer, a collector contact electrode, an ultrathin top-layer silicon drift region, an emitter contact electrode, a gate oxide layer, a poly-silicon gate, P strips and N strips, wherein the N strips are alternatively arranged in the thick silicon layer drift region in longitudinal directions of the P strips. The electric field of the buried layer is improved by employing the ultrathin top layer silicon drift region to increase the longitudinal breakdown voltage of an SOI device; the specific on resistance of the device is reduced by employing the thick silicon layer drift region; and for the ultrathin top layer silicon drift region and the thick silicon layer drift region, lateral linearity variable doping is used for adjusting surface electric field distribution, so that the specific on resistance is greatly reduced as well as high breakdown voltage of the device is greatly maintained.

Patent
03 May 2017
TL;DR: In this paper, a reverse conducting insulated gate bipolar transistor and a manufacturing method for its manufacturing was described. But the method was not applied to the reverse conduction ability of the device.
Abstract: The invention belongs to the field of power semiconductor devices, and particularly relates to a reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor proposed by the invention is characterized in that a P type doping in a junction termination anode area is replaced with an N type doping, so that an N type anode area of a cellular area can be manufactured to be relatively short, thereby improving an anode short-circuit resistance to suppress a Snapback effect; and when a reverse voltage is applied, the N type anode areas of the cellular area and the junction termination area are jointly taken as a cathode of a PIN diode, namely, an area of the junction termination area is utilized for reverse conduction, so while the reverse conduction ability of a device is not effected, the Snapback effect in forward conduction is suppressed. In an actual application, a length of the N type anode area of the cellular area can be flexibly adjusted according to a demand for the forward and reverse conduction abilities of the device to meet the requirement.

Patent
10 Nov 2017
TL;DR: In this article, a horizontal RC-IGBT device with surface dual-gate control is presented, where the starting and closing of the MOS transistor is controlled through a second gate, so as to realize the same functions as those of the conventional structure.
Abstract: The invention discloses a horizontal RC-IGBT device with surface dual-gate control, and belongs to the technical field of a power semiconductor. According to the device, a fly-wheel diode with a conventional structure is connected with a MOS transistor in series; the starting and closing of the MOS transistor is controlled through a second gate, so as to realize the functions which are the same as those of the conventional structure; when the RC-IGBT is in forward operation, the MOS transistor is closed, an N+ collector region in the conventional structure is isolated by the MOS transistor, and at the moment, the device is equivalent to be a pure IGBT, so that a voltage snapback phenomenon in the conventional structure is completely eliminated; when the device is in backward operation, the starting of the MOS transistor is controlled by the second gate, and the fly-wheel diode can work as normal; meanwhile, different from the conventional device with the longitudinal structure, the device disclosed in the invention is the transverse device, the device is established on an epitaxial layer, and a back surface process is not needed for realization of the device, so that the technological difficulty is greatly lowered; and through an RESURF structure, the transverse voltage withstand performance of the device is also reinforced.

Journal ArticleDOI
Shuji Fujiwara1
TL;DR: In this paper, the authors presented an ESD robustness enhancement study of an 800 V junction field effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure.
Abstract: Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure.

Patent
04 Jan 2017
TL;DR: In this article, a gate-grounded N-channel metal Oxide Semiconductor (GGNMOS) was applied to ESD (Electro-Static discharge) protection and a manufacturing method thereof.
Abstract: The invention discloses a GGNMOS (Gate-Grounded N-channel Metal Oxide Semiconductor) device applied to ESD (Electro-Static discharge) protection and a manufacturing method thereof. A P-type doping region is arranged in a drain extension region of a GGNMOS to form a floating reverse diode with a drain NLDD (N-type Lightly Doped Drain) doping region, so that distribution of drain ESD current is changed; ESD leakage current is deviated from the surface of the drain extension region and a conducting channel; the cooling capability during ESD discharge of the GGNMOS is enhanced; secondary breakdown current during snapback of the device is increased; and the ESD protection capability of the GGNMOS device is enhanced.

Proceedings ArticleDOI
01 Sep 2017
TL;DR: A modified two-pin HBM tester has been built that reduces overstressing to a level were valid testing of No Connect pins and high voltage pins with snapback protection is possible.
Abstract: “No Connect” pins were exempted from HBM testing due to tester delivery path parasitics producing an unintended CDM-like overstress. A modified two-pin HBM tester has been build that reduces overstressing to a level were valid testing of No Connect pins and high voltage pins with snapback protection is possible.