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Showing papers on "Snapback published in 2021"


Journal ArticleDOI
TL;DR: In this article, the importance of the intrinsic series resistance effect in the context of resistive random access memory (RRAM) compact modeling is investigated, and a thorough description of the resistance value extraction procedure and an analysis of the connection of this value with the set and reset transition voltages in HfO2-based valence change memories are presented.
Abstract: The relevance of the intrinsic series resistance effect in the context of resistive random access memory (RRAM) compact modeling is investigated. This resistance notably affects the conduction characteristic of resistive switching memories so that it becomes an essential factor to consider when fitting experimental data, especially those coming from devices exhibiting the so-called snapback and snapforward effects. A thorough description of the resistance value extraction procedure and an analysis of the connection of this value with the set and reset transition voltages in HfO2-based valence change memories are presented. Furthermore, in order to illustrate the importance of this feature in the shape of the I–V curve, the Stanford model for RRAM devices is enhanced by incorporating the series resistance as an additional parameter in the Verilog-A model script.

20 citations


Journal ArticleDOI
TL;DR: In this article, a fast switching silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed and investigated, which introduces trench barriers (TBs) at the collector end based on shorted anode (SA) structure to eliminate the snapback effect.
Abstract: A novel fast-switching silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed and investigated in this article. The proposed device introduces trench barriers (TBs) at the collector end based on shorted anode (SA) structure to eliminate the snapback effect. The introduced TB structure can make the flow path of electron current be compressed and extended when the SA LIGBT is turned on so that the opening of collector p+/n-junction is prior to that of collector n+/n-junction. At the same time, it retains the ability to extract unbalanced electrons when the SA LIGBT is turned off. Through the TCAD simulation, the obtained results show that snapback-free can be realized by changing trench depth and pitch between TB structures. Compared with the separated SA (SSA) LIGBT, the forward voltage drop of the proposed LIGBT is reduced by 13.9% with snapback-free and much shorter collector region, which also retains the ability to extract unbalanced electrons. Thus, under the same forward voltage drop of 1.49 V, the turn-off time, and loss of the proposed LIGBT is 20.3% and 21.1% lower than those of the conventional (Conv.) LIGBT, respectively. In general, the tradeoff between turn-off time and forward voltage drop of the proposed LIGBT has much better performance.

17 citations


Journal ArticleDOI
TL;DR: In this article, a novel electrostatic discharge (ESD) protection device based on an n-type metal-oxide-semiconductor field effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a widebandgap material (3.3 eV).
Abstract: A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a wide-bandgap material (3.3 eV). ESD phenomena are important in terms of semiconductor reliability, and the benefits of using 4H-SiC as a material can provide robustness and excellent thermal reliability to ESD protection devices. The proposed device improves the wide range of snapback phenomena caused by the high critical electric field (2.4 MV/cm), in comparison to using Si (0.25 MV/cm); it also improves triggering characteristics and provides a high holding voltage. The proposed device and a traditional silicon-controlled rectifier, a gate-grounded-NMOS, and a gate-body floating NMOS were fabricated using the 4H-SiC process. The electrical characteristics of the experimental devices, determined by a transmission-line-pulsing system, were comparatively analyzed. Additionally, this article presents the analysis of the optimization of electrical characteristics according to the critical design variables of the proposed device, stacking for high-voltage applications, and reliability test results for high temperatures (300–500 K).

16 citations


Journal ArticleDOI
TL;DR: In this paper, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed.
Abstract: 4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

11 citations


Journal ArticleDOI
TL;DR: In this article, an innovative methodology, named AUSBIT (Adelaide University Snap-Back Indirect Tensile test ), is presented to stabilize the disc cracking under diametrical compression, using indirect lateral displacement control.

5 citations


Journal ArticleDOI
TL;DR: In this paper, a simulation study of the off-state breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented, where the dummy gates need to be optimally biased to maximize the breakdown (VBR) and snapback voltages.

5 citations


Proceedings ArticleDOI
21 Mar 2021
TL;DR: In this paper, the behavior of gate grounded vertically stacked nanosheet N-FET (ggNFET) under ESD stress was investigated, and it was found that the sequence of turn-on was dependent on the TLP current ramp rate.
Abstract: The behavior of gate grounded vertically stacked nanosheet N-FET (ggNFET) under ESD stress is investigated in this work. Single Fin (3-Sheet) ggNFET devices exhibit multiple instability points in the TLP-IV characteristic around the snapback region. Each of these instabilities was found to be arising due to non-uniform sheet turn-on and was independent of the presence of body contact. However, this instability was more severe, with a decreased body distance from the source. Furthermore, the sequence of turn-on was found to be dependent on the TLP current ramp rate. A 24-Fin (72 Sheet) ggNFET was simulated to reproduce the current filament like behavior. These 24- Fin simulations revealed a more severe low-current instability due to both non-uniform sheet turn-on and non-uniform Fin turn-on. For a smaller body to source contact distance, this non-uniform turn-on was seen to result in an early failure of the device.

4 citations


Journal ArticleDOI
TL;DR: In this paper, a hybrid source was proposed to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage and current regions that have traditionally been inaccessible due to triggering of the bipolar.
Abstract: A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

4 citations


Journal ArticleDOI
TL;DR: In this article, a dual-MOS-triggered silicon-controlled rectifier (DMTSCR) was developed for high-voltage (HV) electrostatic discharge (ESD) protection.
Abstract: A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( $V_{h}$ ), a strong ESD robustness, and a low $V_{t1}$ , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ $\mu \text{m}^{2}$ . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, $V_{h}$ increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to $0.4~\Omega $ , and the turn-on voltage was clamped at $V_{h}$ . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

3 citations


Journal ArticleDOI
TL;DR: In this article, an RC-IGBT structure with N-Si/n-Ge heterojunction was proposed to suppress the electron flow into the N short region, so the snapback effect can be suppressed.
Abstract: This article proposes an RC -IGBT structure with N-Si/n-Ge heterojunction (NNH-IGBT) to suppress snapback effect. Because the proposed N-Si/n-Ge heterojunction acts as a gradually reverse bias diode to suppress the electron flow into the N-short region, so the snapback effect can be suppressed. For the same ${\mathrm{\scriptstyle {ON}}}$ -state voltage drop ( ${V}_{\text {CE}}$ ), the turn-off loss ( ${E}_{\mathrm{\scriptstyle {OFF}}}$ ) of the NNH-IGBT is lower than the conventional RC -IGBT (Con- RC -IGBT). In addition, the reverse recovery speed of NNH-IGBT is nearly identical to the Con- RC -IGBT. Because of the use of heterojunction, the NNH-IGBT is suitable for operate to suppress the snapback effect, especially at low temperatures.

3 citations


Proceedings ArticleDOI
26 Jul 2021
TL;DR: In this article, the transition phases between snapback and main current flow were adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve were included.
Abstract: Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.

Patent
16 Mar 2021
TL;DR: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components can be integrated along a peripheral region of a high-voltage circuit such as a high side gate driver of a driver circuit as discussed by the authors.
Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

Journal ArticleDOI
TL;DR: This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.
Abstract: To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

Journal ArticleDOI
12 Apr 2021-Silicon
TL;DR: In this paper, the first snapback ambipolar action in gate ground NMOS (GGNMOS) devices close to pinch-off region, which is related with S shaped I-V characteristics under highly injected avalanche generated carriers, was investigated.
Abstract: This paper models first snapback ambipolar action in NMOS, when subjected to high current stress across the drain terminal. We analyze 2 − D ambipolar current in Gate Grounded NMOS (GGNMOS) devices close to pinch-off region, which is related with S shaped I-V characteristics under highly injected avalanche generated carriers. Furthermore, the first snap-back phenomenon in GGNMOS owing to surface bipolarity is investigated. Due to ambipolar current flow and barrier lowering at source-body junction a novel model of surface bipolar activity has been presented. An analytical model for the surface electrostatics is provided and further compared with 2 − D TCAD device simulation results. Moreover, the electron and hole coupling is reported through a simplified model for a complex and distributed 2 − D parasitic bipolar transistor.


Journal ArticleDOI
TL;DR: In this paper, a study of the snapback behavior of reverse conducting IGBTs (RC-IGBTs) by means of 2-D TCAD simulations is carried out, where half-cell TCAD models of 1200-V IGBT structures with different snapback voltage levels were generated by varying the peak doping concentration of the punch-through N-buffer region.
Abstract: In this article, a study of the snapback behavior of reverse conducting IGBTs (RC-IGBTs) by means of 2-D TCAD simulations is carried out. Half-cell TCAD models of 1200-V RC-IGBT structures with different snapback voltage levels were generated by varying the peak doping concentration of the punch-through N-buffer region. First observations show that snapback could be an issue for low current switching commutations of paralleled RC-IGBTs operating at low temperatures, where one device falls back into unipolar mode and current is completely misshared. Results show that the RC-IGBT snapback voltage level, circuit variations, and operating conditions play a critical role for determining whether the parallel RC-IGBTs operate in a stable or unstable mode.

Journal ArticleDOI
TL;DR: In Section I of the above article as discussed by the authors, the sentence beginning in the 18th line of the second column contains typos that misrepresent the range of voltages in a traditional SCR structure.
Abstract: In Section I of the above article [1] , the sentence beginning in the 18th line of the second column contains typos that misrepresent the range of voltages. The correct sentence is the following: “However, the strong snapback characteristics of a traditional SCR structure that are caused by high avalanche breakdown between the well regions allow it to have a substantially high trigger voltage (approximately 17–22 V) and low holding voltage (approximately 2–4 V).”

Proceedings ArticleDOI
19 May 2021
TL;DR: In this article, the authors provided physical insight of zero capacitor RAM based on space charge limited (SCL) model and analyzed the current crowding phenomenon under ambipolar injection from the drain.
Abstract: This paper provides physical insight of ZRAM (Zero Capacitor RAM) based on space charge limited (SCL) model. 2-D NMOS device is characterised and it’s operation area is explored by technology computer aided design (TCAD). In particular, with proper selection of the current ramp at the drain, carrier electrostatics is examined. It analyses the snapback phenomenon in capacitor-less memory under high current application at drain of gate grounded NMOS devices. Physics of current crowding phenomenon under ambipolar injection from the drain is analysed. The work evaluates the electrostatics of the problem in terms of surface and bulk to understand mechanisms of current flow. An analytical model is established to show lesser impact of surface bipolar turn-on under snapback and its larger impact in the bulk impacted by applying bias to the gate.

Proceedings ArticleDOI
05 Jan 2021
TL;DR: In this article, the effects of the substrate doping concentrations of 6H-silicon carbide-based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device on the snapback behavior has been investigated.
Abstract: With the continuous miniaturization of device size, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures. To improve the reliability and robustness of the ICs, ESD protection devices should be used at each I/O pin. In this paper, the effects of the substrate doping concentrations of 6H-silicon carbide-based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device on the snapback behavior has been investigated. The substrate doping concentration is one of the most important design parameters in designing a robust ESD protection device. By utilizing the near punch through effect, the ESD protection characteristics can be improved. We found that the trigger and hold voltages of the snapback curves had increased by increasing the substrate doping concentrations of ggNMOS. The results show that comparatively higher doping concentration can be used to achieve higher trigger and hold voltages which can be used for 5 V applications. All the simulations are carried out using Silvaco ATLAS device simulator.

Patent
19 Jan 2021
TL;DR: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components can be integrated along a peripheral region of a high-voltage circuit such as a high side gate driver of a driver circuit as discussed by the authors.
Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Proceedings ArticleDOI
26 Sep 2021
TL;DR: In this article, a hybrid finite difference model for SCRs and open base transistors with a lowly doped region is presented, which solves the diffusion and transport equation in a spice simulator.
Abstract: A hybrid finite difference model for SCRs and open base transistors with a lowly doped region is presented. It solves the diffusion and transport equation in a spice simulator. The results are compared with VF-TLP measurements for different rise times and different lengths of the lowly doped region of the devices. A good agreement of the simulated and measured quasi-static and peak voltage is achieved.

Proceedings ArticleDOI
15 Sep 2021
TL;DR: In this article, the ESD-ability effect of parasitic p-type Schottky diodes on the high-voltage pLDMOS is evaluated using the TLP testing machine, which can be used to analyze the component of snapback I-V measurement values such as component trigger voltage (V t1 ), holding voltage (v h ), and secondary breakdown current (I t2 ) data.
Abstract: The ESD-ability effect of parasitic p-type Schottky diodes on the high-voltage pLDMOS is evaluated in this paper. By using the TLP testing machine, it can be used to analyze the component of snapback I-V measurement values such as component trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ) data. Finally, it can be found that this parasitic Schottky device structure can be regarded as adding a reverse Schottky diode in series at the drain-end of the reference device. In this way, the on-resistance of the component increases, and the trigger voltage (V t1 ) tends to be increased too. It is also found that as the area ratio (>85%) of the reverse Schottky diode of the drain-end increases, the current density at the drain terminal becomes more dispersed. Then, the immunity of components to ESD is also significantly improved.

Proceedings ArticleDOI
09 Jul 2021
TL;DR: In this paper, a Gate-Controlled DDSCR with MOS-path (EMGC-DDSCR) is proposed for high and adjustable holding voltage, which reduces surface current and artificially lengthens the SCR path in longitudinal direction without consuming extra layout.
Abstract: High-voltage power integrated circuits such as automotive electronics and power management have become a significant branch of semiconductor industry. Faced with harsh working environment, high-voltage power integrated circuits generally require robust electrostatic discharge (ESD) protection schemes. However, the deep snapback of traditional Silicon Controlled Rectifiers (SCR) gives rise to a low holding voltage, implying they cannot be directly applied for high-voltage ESD protection due to CMOS latch-up. Based on above issues, this paper proposes a Gate-Controlled DDSCR embedded with MOS-path (EMGC-DDSCR) for high and adjustable holding voltage. The electric field of polysilicon gates push ESD current into deeper discharging path inside the device, which reduces surface current and artificially lengthens the SCR path in longitudinal direction without consuming extra layout. Theoretically, holding voltage is increased while high failure level of the device is maintained. A typical numerical model of SCR holding voltage is constructed and analyzed. The channel conduction of EMGC-DDSCR is altered by changing cathode MOS gate bias, which affects positive feedback of the SCR structure. The adjustable holding voltage is thus achieved. Two SCR structures in this paper are designed based on 0.18μm standard BCD process design rules. Silvaco TCAD platform is utilized to perform two-dimensional DC scanning simulation and TLP transient simulation on both devices. Simulation results are well consistent with theoretical analysis, which provides a new idea for HV SCR design with a single structure suitable for multiple ESD windows.

Patent
21 Jan 2021
TL;DR: In this article, an ESD protection device with the mechanism of punch through to achieve low trigger voltage is presented. And the structure of ESD-protection device includes parasitic NPN and parasitic PNP.
Abstract: The present invention provides an ESD protection device with the mechanism of punch through to achieve low trigger voltage. At the same time, the structure of ESD protection device includes parasitic NPN and parasitic PNP. Parasitic NPN and parasitic PNP will form a silicon controlled rectifier (SCR) device with snapback behavior to increase the protection capability of ESD protection device.

Proceedings ArticleDOI
10 May 2021
TL;DR: In this paper, a detailed TCAD simulation study of Snapback in 33V and 5V Inverters from a high performance grade-0 automotive 018um BCD technology is presented.
Abstract: Voltage Stress (Vstress), a critical integrated circuit (IC) automotive reliability test screen, can be as high as 15Vddmax at 150C This work summarizes a detailed TCAD simulation study of Snapback in 33V and 5V Inverters from a high performance grade-0 automotive 018um BCD technology These results demonstrate that Well (Body) tie spacing of NMOS and PMOS is critical in preventing Snapback during high temperature (150C) high voltage (15Vddmax) Vstress tests Therefore, an aggressive Well-tie spacing design rule incorporated during the initial technology development is required to ensure Snapback robustness for such Vstress reliability testing