Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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22 Oct 2007
TL;DR: In this paper, a comparative analysis between transient triggered and voltage referenced ESD power clamps is presented, with both external and internal breakdown voltage reference techniques leading towards both optimal snapback characteristics and a small footprint ESD protection solution for power management applications.
Abstract: The results of a comparative analysis between transient triggered and voltage referenced ESD power clamps are presented. Different architectures with both external and the internal breakdown voltage reference techniques are studied leading towards both optimal snapback characteristics and a small footprint ESD protection solution for power management applications. The physical mechanism of ESD snapback operation is discussed in terms of the classical understanding of avalanche-injection conductivity modulation in a bipolar transistor. The advantage of an internal Zener diode solution over both an enhanced Zener and a BVCER clamp is demonstrated.
2 citations
26 Jul 2021
TL;DR: In this article, the transition phases between snapback and main current flow were adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve were included.
Abstract: Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.
2 citations
Patent•
01 Aug 2014
TL;DR: In this paper, an ESD protection circuit includes a voltage detecting unit, an inverting circuit, a snapback generating unit and a holding voltage control unit, which is used to adjust the holding voltage when detecting a voltage variation between the first power line and the second power line.
Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a voltage detecting unit, an inverting circuit, a snapback generating unit and a holding voltage control unit. The voltage detecting unit outputs a control signal according to a voltage between a first power line and a second power line, wherein the first power line has an operation voltage. The inverting circuit is used for receiving the control signal and accordingly outputs a trigger voltage. The snapback breakdown generating unit has a first transistor device. The holding voltage control unit which has a second transistor device is used for adjust a holding voltage, wherein a type of the transistor device is as the same as the high voltage transistor. When detecting a voltage variation between the first power line and the second power line, the snapback breakdown generating unit and the holding voltage control unit is triggered by the inverting circuit, and makes the holding voltage be larger than the operation voltage as snapback breakdown of the snapback breakdown generating unit happens.
2 citations
18 Oct 2004
TL;DR: In this paper, the lateral dimensions of an LVTSCR-based ESD cell were optimized for different operational conditions and ultimate on-chip BSD protection schemes extendable to a variety of technologies.
Abstract: Optimization of the lateral dimensions of an LVTSCR-based ESD cell allows flexible tuning of the I-V characteristics and maximization of the cells' performance under snapback conditions during the high current regime of an HSD event Once the trigger point is reached and the voltage snaps back, the holding voltage is dependent on lateral arrangement of the wells' implantations and changes in the cell's interconnections Appropriate choices of these dimensions and interconnections permit design of tunable high holding voltages over a wide range This paper presents the design optimization method and I-V characteristics of cells fabricated for different operational conditions and ultimate on-chip BSD protection schemes extendable to a variety of technologies
2 citations
17 Apr 2005
TL;DR: In this paper, a high voltage power supply ESD protection element containing a high-voltage VDMOS which is designed to survive bipolar snapback has been presented, and it operates as an active clamp for low currents, and for high currents, the parasitic vertical bipolar transistor conducts the current.
Abstract: The paper presents a high voltage power supply ESD protection element containing a high voltage VDMOS which is designed to survive bipolar snapback. For low currents, it operates as an "active clamp", and for high currents, the parasitic vertical bipolar transistor conducts the current. The snapback current level is higher than 250 mA for (transient) latch-up safety during normal operation.
2 citations