Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Interaction of RF DPI with ESD Protection Devices in EMS Testing of IC Chips

Abstract: Semiconductor integrated circuit (IC) chips are tested with intentional radio frequency (RF) disturbance under the direct power injection (DPI) method of IEC62132-4 for immunity. The paper exhibits on-chip waveforms measured at some points on the Si substrate nearby electrostatic discharge (ESD) protection devices at the IC pin of interest, which are the very first devices responding to RF power during DPI. The chip ESD compact model (CECM) captures the whole response in simulation, including snapback current-voltage transfer characteristics of the protection devices, Si substrate coupling around the devices and chip-package-printed circuit board (PCB) interaction. The measurements and simulation are correlated for a wide range of 30 dB RF power, with Silicon test chips in a 0.13 μm Bipolar/CMOS/DMOS (BiCD) technology. The CECM technique can be extended toward full-chip and system-wide electromagnetic susceptibility (EMS) simulation of electronic systems.

On the ESD behavior of pentacene channel organic thin film transistors

Abstract: Detailed physical insight into the ESD behavior and unique failure mechanisms of Pentacene Organic Thin Film Transistors (OTFTs) is reported. Orders of magnitude difference in channel current under ESD time scales, when compared to DC time scales, is discovered. Moreover, unique three stage TLP characteristics with snapback state and novel failure mechanism are reported. Finally, influence of channel field and Surface Assembled Monolayer (SAM) on the carrier transport and failure threshold is addressed.

Origin of It2 drop depending on process and layout with fully silicided ggMOS

Abstract: Source-drain process optimization and a diffusion layout technique enable reduction of the snapback voltage (Vt1). Lowering Vt1 of the fully silicided ggMOS enabled low on-resistance and a higher failure current (It2) combined stably in multi-finger turn-on operation. Moreover, to meet both hot-carrier reliability and the ESD requirement, lightly doped drain (LDD) process was obtained.

Statistical Learning of IC Models for System-Level ESD Simulation

Abstract: To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.