Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Antifuse programming circuit with snapback select transistor

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Modelling of breakdown voltage in sub-micron SOI transistors

Abstract: Model validation for submicron SIMOX (separation by implantation of oxygen) transistors by careful comparison of the simulated and measured snapback voltages as a function of gate length is reported. The transistors were fabricated in SIMOX material with an estimated film thickness of 0.2 mu m, a buried insulator thickness of 0.4 mu m, and a gate oxide thickness of 20 nm. The measured threshold voltage of the 1 mu m n-channel transistor was 1.08 V and the subthreshold slope 86 mV/decade. The snapback voltage was defined as the maximum drain voltage at which the transistor turns off, when swept in the direction of decreasing gate voltage. Excellent agreement has been achieved over a range of transistor gate lengths down to 0.5 mu m. Two-dimensional device simulation can be used to determine the optimum transistor structure by considering the factors associated with engineering both the source and drain regions with a view to maximizing the breakdown voltage. >

Comparison of breakdown characteristics of DeNMOS devices with various drain structures

Abstract: In this work, OFF-state breakdown characteristics of shallow trench isolation (STI)-type drain extended NMOS (DeNMOS) devices with different drain structures are studied and compared The drain structures include deep-drain structure and structures with heavy doping on STI-sidewall regions These devices show improved ON-state resistance without degrading breakdown voltage Devices with higher doping underneath the drain diffusion region exhibit stronger bipolar triggering and higher snapback in their breakdown characteristics, thereby sustaining higher drain current levels before device failure The devices with heavy doping only on the STI-sidewall show intermediate snapback characteristics between conventional and deep-drain devices in the breakdown region Therefore, this work provides physical insights into the impact of different drain doping profiles on low-voltage I-V characteristics and high current drain breakdown characteristics of STI-DeMOS devices for different drain doping profiles

Physics & Modeling of Ambipolar Snapback Behavior in Gate Grounded NMOS

Abstract: This paper models first snapback ambipolar action in NMOS, when subjected to high current stress across the drain terminal. We analyze 2 − D ambipolar current in Gate Grounded NMOS (GGNMOS) devices close to pinch-off region, which is related with S shaped I-V characteristics under highly injected avalanche generated carriers. Furthermore, the first snap-back phenomenon in GGNMOS owing to surface bipolarity is investigated. Due to ambipolar current flow and barrier lowering at source-body junction a novel model of surface bipolar activity has been presented. An analytical model for the surface electrostatics is provided and further compared with 2 − D TCAD device simulation results. Moreover, the electron and hole coupling is reported through a simplified model for a complex and distributed 2 − D parasitic bipolar transistor.