Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Modeling and Simulation of Parasitic NPN ESD

Abstract: Electro-Static Discharge (ESD) is critical for the reliability of integrated circuits. Applying ESD model in circuit simulation could help to predict and avoid potential failure caused by ESD. This paper proposes a SPICE macro model for parasitic NPN ESD and related methods for extracting SPICE model parameters. The macro model utilizes the Taylor series to express collector current of NPN transistor under avalanche breakdown, and thus solves the problem of lack of convergence in prior models. The macro model’s parameters are obtained by device measurement together with curve fitting. A device with parasitic NPN was fabricated in SMIC with 0.18um BCD process to verify the macro model. Chip tests indicate that the simulation results of the device’s macro model exactly match with the real ESD characteristics of the device, which demonstrate the validity of the macro model for parasitic NPN ESD behavior in circuit simulations. Introduction ESD (Electro-Static Discharge) is a serious threat to the reliability and yield of integrated circuits. ESD stress currents flowing into internal circuits may cause unrecoverable damage, so it is necessary to provide ESD protection to integrated circuits [1-6]. At present, ESD stress tests are performed during trial manufacture. If these tests are failed, a conventional approach to response is investigating the cause of the ESD damage and reexamining the design rule and process conditions. Such approach leads to high expense and time waste. Therefore, it is important to predict ESD behavior, potential failure and test damage resistance before trail manufacture. Performing ESD simulation to protection circuits during circuit design and layout is an effective approach for solving the foregoing problem [7, 8]. This paper presents a SPICE macro model for NPN ESD. The SPICE model parameters are extracted based on ESD device measurement. The macro model is verified by experimental data which demonstrates the validity of the macro model for NPN devices in ESD circuit simulations. An Equivalent Circuit for a Parasitic NPN ESD Fig. 1(a) shows a cross-sectional diagram of a typical parasitic NPN ESD in a BCD process, Fig. 1(b) shows an equivalent circuit of the parasitic NPN ESD, comprising an NPN transistor Q1 and some parasitic elements. Dnws refers to the parasitic diode between the N-well and P-substrate. Rsub refers to the parasitic resistor in the P-substrate. Rbase refers to a total base resistance, equaling to a sum of resistances of the Pbase resistor and contact resistor. Rc and Re respectively refer to the parasitic resistor of collector and the parasitic resistor of emitter. The on-resistance Ron in the high current linear region after device snapback is approximately complied to the following equation, Ron=Rc+Re. Iaval refers to a controlled current source to represent the hole injection current when the C-B junction is under avalanche breakdown region. 6th International Conference on Information Engineering for Mechanics and Materials (ICIMM 2016) © 2016. The authors Published by Atlantis Press 413 c aval I M I ) 1 ( − = (1) (a) Cross section (b) its equivalent circuit Fig. 1. A typical Parasitic NPN ESD Where M is the avalanche multiplication factor [9] n cb cb BV V M ) / ( 1 1 − = (2) Vcb refers to a biased voltage on the C-B junction and BVcb represents a breakdown voltage of C-B junction. Avalanche Multiplication Directly applying formula (1) or (2) into prior SPICE simulators returns an incorrect result indicating that a snapback phenomenon emerges. The reason is that when Vcb BVcb, and M∝, the simulating result is lack of convergence. Thus an adjustment to formula (1) is necessary for obtaining a convergent result of SPICE simulation. ) exp(m M = (3) Wherein ) ) ( 1 ln( ) ) ( 1 1 ln( n cb cb n cb cb BV V BV V m − − = − = (4) According to the Taylor series 2 3 ln(1 ) 2 3 x x x x − = − − − − for 1 < x (5) The m could be expressed as 2 3 1 1 1 2 3 n n n xn

Measurements of the persistent current decay and snapback effect in Nb3Sn Fermilab-built accelerator prototype magnets

Abstract: In recent years, Fermilab has been performing an intensive R an D program on Nb{sub 3}Sn accelerator magnets. This program has included dipole and quadrupole magnets for different programs and projects, including LARP and VLHC. A systematic study of the persistent current decay and snapback effect in the fields of these magnets was executed at the Fermilab Magnet Test Facility. The decay and snapback were measured under a range of conditions including variations of the current ramp parameters and flattop and injection plateau durations. This study has mostly focused on the dynamic behavior of the normal sextupole and dodecapole components in dipole and quadrupole magnets respectively. The paper summarizes the recent measurements and presents a comparison with previously measured NbTi magnets.

Comparison of flight and ground data for radiation-induced high current states in the 68302 microprocessor

Abstract: It has been observed that the 68302 microprocessor, which is being flown on several space vehicles, has not shown signs of experiencing either single event latchup (SEL) or single event snapback (SES) as would have been predicted using ground-based test data. This study presents the comparison of the flight to ground data.

Novel bidirectional electro-static discharge (ESD) device and fabrication method thereof

Abstract: The invention discloses a novel bidirectional electro-static discharge (ESD) device and a fabrication method thereof. The ESD device comprises a semiconductor substrate, a P well, an N well, an NPN triode structure, a bidirectional diode structure and ESD implantation layers, wherein the P well is arranged in the semiconductor substrate, the N well is generated at one side of the P well, the NPN triode structure is arranged at the other side of the P well, the bidirectional diode structure is arranged in the N well, and the ESD implantation layers are arranged under a collector and an emitter of the NPN triode structure. By injecting P-type ESD_IMP to parts below the collector and the emitter of an NPN triode of the ESD device, a trigger voltage of an NPN snapback effect of a vertical direction is further reduced, so that the purpose of reducing the trigger voltage of the whole electro-static protection structure is achieved. The NPN device has a bilateral symmetric structure, and the ESD device has bidirectional discharge capability by bidirectional diodes which are externally connected in parallel.

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Abstract: An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.