Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Trends in VLSI processing

Abstract: The scaling laws for MOS transistors are briefly reviewed and physical limitations like velocity saturation and mobility degradation are explained. The maximum operating voltage is limited by substrate currents, hot carrier effects, punchthrough and snapback phenomena. The problem related to the increasing interconnect delay time is mentioned. Trends in CMOS and BICMOS are pointed out and the choice between p-well, n-well or twin well is discussed. A few remarks are made about the SOI technology (Silicon On Insulator). Finally some new developmentsin micropatterning and in VLSI materials such as silicides and refractory metals are addressed and their implemention in full process is discussed.

Physical effect on transition from blocking to conducting state of barrier-type thyristor

Abstract: The transition of the barrier-type thyristor (BTH) from blocking to conducting-state occurs between two entirely contrary physical states with great disparity in nature The physical effects and mechanisms of the transition are studied in depth The features of the transition snapback point are analyzed in detail The transition snapback point has duality and is just the position where the barrier is flattened It has a significant influence on the capture cross-section of the hole and high-level hole lifetime, resulting in the device entering into deep base conductance modulation The physical nature of the negative differential resistance segment I−V characteristics is studied It is testified by using experimental data that the deep conductance modulation is the basic feature and the linchpin of the transition process The conditions and physical mechanisms of conductance modulation are investigated The related physical subjects, including the flattening of the channel barrier, the buildup of the double injection, the formation of the plasma, the realization of the high-level injection, the elimination of the gate junction depletion region, the deep conductance modulation, and the increase in the hole's lifetime are all discussed in this paper

Fuse-type memory cells based on irreversible snapback device

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

TVS (Transient Voltage Suppressor) device with low residual voltage, high surge and one-way snapback and manufacturing method thereof

Abstract: The invention discloses a TVS (Transient Voltage Suppressor) device with low residual voltage, high surge and one-way snapback and a manufacturing method thereof. The device comprises an N-type substrate, and is characterized in that a P-type epitaxial layer is arranged on the N-type substrate, the P-type epitaxial layer is provided with an SN layer and an SP layer, the SN layer and the SP layer are isolated by a deep trench. The device provided by the invention not only reduces the breakdown voltage, but also greatly improves the peak current IPP in the breakdown direction while providing lowleakage current. Meanwhile, the device reduces the clamping voltage in the positive conduction direction and the negative breakdown direction, so that the protected device is completely located in asafe area. The device has the advantages of high power, low cost and the like.

Snapback-free and low-loss SAG-LIGBT with self-driving auxiliary gate

Abstract: A novel snapback-free and low-loss shorted-anode lateral insulated bipolar transistor (SA-LIGBT) based on silicon on insulator with self-driving auxiliary gate (SAG) in the anode is proposed, named as SAG-LIGBT. The SAG is characterised by metal oxide semiconductor (MOS) structure in the anode, and the gate of the MOS is shorted with the anode electrode, thus self-driving without extra gate signal is achieved. At anode voltage V A = 0, the P-base serving as a barrier to hinder electrons flowing into the N + anode. At V A = V on of the forward conduction, the P-base is depleted to intrinsic, and the anode resistance R SA is increased from R P-base to R intrinsic. At V A = V bus of the turn-off state, the P-base is fully depleted and an electron accumulation layer is formed under the SiO2, thus the R SA is decreased from R intrinsic to R n-channel to provide a low-resistance path for electron current. Consequently, the device not only eliminates the snapback effect but also reduces the turn-off energy loss E off. Therefore, a better trade-off is obtained between V on and E off. At the same V on, the E off of SAG-LIGBT is decreased by 57 and 66% compared with separated shorted-anode LIGBT (SSA-LIGBT) and SA-LIGBT, respectively. Moreover, the SAG-LIGBT exhibits the shorter T off of 80 ns than the SSA-LIGBT and vertical P-collector and N-buffer LIGBT at J A = 100 A/cm2.