Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Electronic device and method for reading data stored in resistive memory cell

Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells arranged in a plurality of columns and a plurality of rows, the plurality of resistive memory cells having a snapback characteristic; and a read circuit configured to apply a read voltage to a memory cell selected among the plurality of resistive memory cells, and sense data stored in the selected memory cell by determining whether or not a snapback phenomenon has occurred in the selected memory cell, wherein the read voltage has a level higher than a level of a first voltage and lower than a level of a second voltage, wherein the snapback phenomenon occurs when the first voltage is applied to the selected memory cell in a case where the selected memory cell stores first data, and wherein the snapback phenomenon occurs when the second voltage is applied to the selected memory cell in a case where the selected memory cell stores second data.

ESD MOSFET model calibration by differential evolutionary optimization algorithm

Abstract: The aim of this paper is to present the utilization of modern optimization algorithm called Differential Evolution to automatically fit the measured data from test chip to the appropriate electrostatic discharge (ESD) model without the need of manual model-parameters tuning. In contrast with proposed method the traditional approach can be very time and resource consuming. To the best knowledge of the authors, this novel approach has never been previously used. Short introduction to ESD NMOST function and properties are presented along with basic overview of differential evolutionary optimization algorithm. Results of fitting the technology-optimized macro-model of NMOST to the simple piece-wise linear model of MOSFET snapback I-V characteristic will be presented.

Research and optimization of the ESD response characteristic in a ps-LDMOS transistor

Abstract: The ESD response characteristic in a p-type symmetric lateral DMOS (ps-LDMOS) has been investigated. The experimental results show that the ps-LDMOS has weak ESD robustness due to an absence of the "snapback" characteristic. In addition, the location of the hot spot changes little for the special device. The method for reducing the lattice temperature of the hot spot can be used to enhance the ESD capacity of the ps-LDMOS, thereby, a novel and easily-achievable ps-LDMOS structure with a p-type lightly doped drain (p-LDD) has been proposed. The special region p-LDD lowers the electric field at the edge of the poly gate, making the whole distribution of the surface electric field more uniform. Therefore, the ESD robustness is improved two times and no obvious change of other electric parameters is introduced.

A Snapback Evaluation Technique for Synthetic Lines

Abstract: : A technique is proposed for quantifying the amount of energy released when synthetic lines fail and recoil, called snapback. Ten synthetic line material/construction combinations are investigated by bending the line around a 1 in. diameter pin fixture and loading until failure occurs at the pin. High-speed photography is used to calculate the velocity of the line at failure and the attending kinetic energy. Three parameters are proposed to quantify snapback; (a) the Storage Energy Potential is a measure of how much energy a line stores as load is applied to it, (b) Snapback Energy Potential is a measure of the kinetic energy that the line possesses after failure occurs and the line recoils, and (c) the Energy Release Ratio indicates the proportion of stored energy that becomes kinetic energy after the line parts. In addition to discussing the evaluation technique, the various lines tested are compared to determine if some materials or constructions have a lower potential to snapback. The failure mechanism (i.e., the sequence of yarn failures that culminate in complete failure) of each line construction is observed using high-speed photography to determine if lines with a cascading failure mechanism (i.e., failure over a relatively long period of time) have lower snapback potential. The path that a line follows during snapback is also observed. Lines snap back directly toward the fixed end if the failure occurs in clear line. If a line retracts around the curved surface as a bollard, significant lateral velocity is imparted to the line and it sweeps a wide area.