Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Snapback and overprogramming modeling using finite-element electrothermal simulation

Abstract: We present a new model for the simulation of negative differential resistance (?snapback?) in a phase-change memory cell using an electrothermal finite-element iterative calculation implemented in ANSYS. This model improves upon our previous models by applying a double Arrhenius temperature-dependent resistivity for the amorphous chalcogenide, and a JMAK (n=3.5) model to describe the phase-change kinetics. As a result, the model captures the possibility of partial crystallization during typical pulsed heating conditions, a crucial factor in determining the abruptness of snapback. In addition to fitting our experimental data, the model is capable of predicting and characterizing the onset of overprogramming. Overprogramming occurs when the process of crystallizing some parts of the initially amorphous region leads to other parts heating above the melting point, leading to a remnant amorphous portion that limits the reduction of the cell?s resistance. The paper also explores the impact of initial amorphous size as well as the presence of a defect breaking the symmetry of the amorphous hemisphere.

Gate burnout of small signal MODFET's at TLP stress

Abstract: The gate burnout of GaAlAs/GaAs and pseudomorphic InGaAs channel on GaAs substrate MODFETs have been studied at the gate 10 ns transmission line pulse overstress. The snapback gate-drain pulse characteristic is measured. Using 2-D numerical simulation it is shown, that the snapback mechanism is the double avalanche injection current instability and filamentation in the MODFET's nondoped layers.

To achieve a novel weak snapback characteristic in the high voltage nLDMOS

Abstract: A drain-side engineering to LDMOS by doping concentration and length modulations of the N-type adaptive layer to obtain weak snapback characteristic nLDMOS are presented in this work It's a novel method to reduce trigger voltage(V t1 ) and to increase holding voltage(V h ) These efforts will be very suitable for the HV power management IC applications Meanwhile, in this work, we will discuss trigger voltage, holding voltage and R on resistance distribution of these novel HV nLDMOS devices

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Abstract: In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.