Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability

Abstract: The electrostatic discharge (ESD) failure threshold of an output buffer is observed to be sensitive to the used-gate finger number. It is found that the lower the current drive capability, the lower the ESD failure threshold, and the damage sites of the output buffer are always located at the used gate n-channel metal-oxide semiconductor (NMOS) transistors. This observation can only be explained on the basis of the energy dissipation (E=VSP×ID×time) in each finger, where ID is composed of channel current and bipolar current. From the real-time current-voltage measurement during ESD zapping, three phenomena are observed. The first is that a transistor with a floating gate (used-gate fingers) has a larger snapback voltage (VSP) than that with a grounded gate transistor. The second is that due to the accumulation of hot holes in the floating gate, a constant gate voltage can be induced during the ESD zapping. The last is that this induced-gate-voltage can assist the switching on of the NMOS transistors and reduction of the ESD duration. Therefore, the ESD duration of a transistor with high current drive capability will be much shorter than that of low current drive capability. As a result, high current drive capability leads to a high ESD failure threshold.

Control method of IGBT chip

Abstract: The present invention discloses a control method of an IGBT chip. The control method of the IGBT chip is characterized in that when an IGBT is in the positive conduction, a control switch Q is in a turn-off state, a PN junction J2 is in a reverse bias state, a PN junction J1 is in a positive bias state, and an electric field does not influence an electrode N2 because of the effect of an isolating cover; when the IGBT is located in the reverse conduction, the control switch Q is in a turn-on state, the PN junction J1 is in the reverse bias state, the PN junction J2 is in the positive bias state, and after flowing out to be blocked by the influence of a P potential barrier, the electrons move towards the electrode N2 , and move and flow out via the control switch Q. The control method of the IGBT chip of the present invention solves the snapback basically while not influencing the performance parameters, and enables a diode to be integrated in the IGBT effectively, thereby really realizing the situation that the IGBT has the low forward voltage drop and also has a good switching speed, and improving the reliability of a device.

Utilizing design of experiments, Monte Carlo simulations and partial least squares in snapback elimination

Abstract: The first test structures built on a newly developed semiconductor process revealed that product could be susceptible to an operational fault called the snapback condition. The process architect identified five factors that might be adjusted to greatly reduce the occurrence of snapback. A response surface type of experiment was run on the process simulator so that the ideal combination of settings for these five factors could be identified. Monte Carlo simulations were then run at the new settings for those process factors. The data from the Monte Carlo simulations were analysed using partial least squares to identify the process variables that would be most critical to control in maintaining a snapback-resistant process. The new settings were confirmed on actual product. © 1998 John Wiley & Sons, Ltd.

ESD induced damage and hot-carrier reliability of NMOS and PMOS transistors

Abstract: The Hot-Carrier Induced (HCI) degradation and the Electro-Static Discharge (ESD) induced damage are characterized for evaluating the reliability of both submicron LDD NMOS and PMOS transistors. These two types of transistors show different reliability behaviors in terms of the maximum HCI degradation conditions, the DC lifetimes, the snapback voltage characteristics, and ESD failure threshold voltages. Some observations are also described as unique features in the geometric effects both for HCI degradations in short channel/narrow width regimes and for ESD failure thresholds in the Machine Model (MM) ESD device characterization.

Characterization of dynamic spatial conduction patterns on ESD protection circuitry by photon-counting imaging

Abstract: A photon-counting imaging method has been effectively employed to acquire the extremely weak pulse electroluminescence from a thick-field-oxide electrostatic discharge (ESD) protection device during very short pulse stressing. From this, its dynamic spatial conduction patterns with respect to different currents, pulse widths, and repetition rates could then be directly visualized and assessed. The authors have applied such an imaging method successfully in the acquisition of a full series of spatial pulsed emission patterns on circuitry during ESD simulation. This could offer a means for direct, simultaneous observation of emerging failure on such a device. The exact sequential turning-on nature of bipolar NPN snapback, on each ladder-channel and its non-uniformity in spread during different levels and widths of pulsation could also be resolved directly. The authors report on the accurate determination of the site of the resistive short on failed samples by this technique. >