Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Two-channel RC-LIGBT device and manufacturing method thereof

Abstract: The invention belongs to the power semiconductor integration circuit field and especially relates to a transverse reverse conducting insulated gate bipolar transistor (Reverse Conducting-LIGBT, RC-LIGBT) and a manufacturing method thereof. The device and the method are used for restraining a snapback phenomenon of a traditional RC-LIGBT device, simultaneously improving a reverse direction diode characteristic and increasing stability and reliability of the device. By using the RC-LIGBT device, through introducing a composite structure into a collector electrode terminal of the device to form a one-way conductive path possessing two channels, under a forward direction LIGBT work mode, an influence of an N-type collecting zone on a conduction characteristic is completely shielded, the snapback phenomenon is completely eliminated, a low conduction voltage drop which is the same with the voltage drop of a traditional LIGBT is possessed and stability and reliability of the device are increased. Simultaneously, under a reverse direction diode follow current work mode, two follow current channels are provided on the collector electrode terminal, a follow current capability is optimized and a small conduction voltage drop is possessed.

High voltage bipolar-based esd protection structure

Abstract: PROBLEM TO BE SOLVED: To provide an area-efficient, high voltage, single polarity ESD protection device.SOLUTION: An ESD protection device 300 includes: a p-type substrate 303; a first p-well 308-1 formed in the substrate and sized to contain n+ and p+ contact regions 310, 312 that are connected to a cathode terminal; a second, separate p-well 308-2 formed in the substrate and sized to contain only a p+ contact region 311 that is connected to an anode terminal; and an electrically floating isolation structure 304, 306, 307-2 formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snapback mode to provide a low impedance path through the structure for discharging an ESD current.

Semiconductor device having esd protecting element

Abstract: PROBLEM TO BE SOLVED: To provide an ESD (Electro Static Discharge) protecting element of a semiconductor device having a structure actualizing desired ESD resistance without impairing linearity of capacitance variation of a variable capacitance element. SOLUTION: The variable capacitance element of an oscillation circuit is constituted by having a first N type region enclosed with an element isolation region, a first high-density P type region below the element isolation region, a first P type region contacting the first N type region to form a PN junction, and a second N type region formed opposite the first N type region with the element isolation region interposed, and connecting the first P type region to a ground potential and the first N type region to a control voltage. The first N type region, first high-density P type region, and second N type region constitute a snapback transistor as an ESD protecting element by connecting the second N type region to the ground potential. COPYRIGHT: (C)2009,JPO&INPIT

RF LDMOS with excellent robustness for wideband application

Abstract: A RF LDMOS with an additional P-type implant below channel region is presented to achieve high ruggedness. With the help of this implantation, the device shows significantly improved snapback performance. Besides on-wafer TLP test, we propose a more rigorous ‘open’-circuit test to demonstrate this fantastic robustness. The Faraday shield and drift region is finely engineered to achieve optimum Rds(on)-BV trade-off. A 1um-drift length device is shown to achieve more than 300mA/mm saturation current and 1.6W/mm power density at 1dB compression, while maintaining HCI immunity. A power amplifier is implemented from 400MHz to 470MHz to verify the broadband performance.

Enhanced PMOS-triggered PMLSCR with robust EOS immunity

Abstract: An enhanced PMOS-triggered PMLSCR is proposed. Under the condition that both PNP and NPN BJT's are triggered simultaneously, voltage overshoot and turn-on uniformity can be further improved. From TCAD simulation, it is clear that with the help of trigger current, conduction path of SCR goes deeper and snapback voltage is reduced. By the designed power sequence, holding voltage and current of SCR devices considering self-heating effect are attained. Robust EOS immunity can be assured accordingly.