Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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Dissertation•
05 May 2020
TL;DR: The SOA sub-project is designed to describe the functional safety area of nanoscale SiGe:C HBTs allowing the compact model to take into account critical aspects, and an aging model is developed to account for the wear-out mechanism occurring in that operation regime.
Abstract: The development of new BiCMOS technology will be possible, thanks to the SiGe:CHBTs technological improvements to reach dynamic performance beyond 0.5 THz. Animportant aspect to be investigated is the Safe Operating Area (SOA) beyond the traditionalBVCEO. In fact, due to the complexity of future architectures of HBTs (likethe B55X from STMicroelectronics) and their nanoscale size, an increase of the wear-outmechanisms occurring in these transistors is expected. In addition, because of the increasingdependence of circuit design on software tools, it is expected that additional effortswill be required to develop more predictive compact models. Thus, the SOA sub-projectis designed to describe the functional safety area of nanoscale SiGe:C HBTs allowing thecompact model to take into account critical aspects.After a short introduction, a precise description of the transistor operations beyondthe breakdown voltage is detailed in the second chapter. The compact model HICUM isimproved to account for the mechanisms occurring in this region to accurately model theavalanche regime and the pinch-in effect. This new model is validated on TCAD simulationsand through electrical measurements on different devices, architecture, geometriesand temperatures.In the third chapter, the investigation is deepen towards the device border’s operation.A study of the pinch-in effect and the snapback behavior is therefore realized to understandthe operation limitations at high currents and voltages and a stable operation regime isintroduced.In the fourth chapter, accelerated aging tests are carried out at the boundaries of thesafe operating area to submit the transistor to thermal and hot carriers stresses during itsoperation. An aging model is developed to account for the wear-out mechanism occurringin that regime.To conclude, this work allowed to increase the modeling of SiGe HBTs at high voltagesand currents accounting for the wear-out mechanisms occurring in that operation regime.
1 citations
TL;DR: In this paper, a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with separated free-wheeling diode (FWD) is proposed, and the results show that the new structure achieves snapback-free characteristics.
Abstract: A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring separated free-wheeling diode (FWD) is proposed. The snapbacks of conventional RC-IGBT are analysed; the electrical characteristics for the proposed RC-IGBT with four kinds of anti-paralleled FWDs are discussed. The results show that the new structure achieves snapback-free characteristics. Moreover, the figures of merit I (FOM I) between V F and E off in the forward operation case and FOM II between V R and Q rr in the reverse operation case are superior to conventional RC-IGBT. Especially for the integrated merged P-i-N/Schottky (MPS, FWD-A), FOM I can be enhanced by 10%, and FOM II can be enhanced by 50%. In addition, the technological ease of fabrication is another attraction of the proposed device.
1 citations
TL;DR: In this article, the authors proposed an N-path SA-IGBT, which is partially surrounded by the floating P-layer and oxide layer in the backside of the wafer, which provides a direct path to the N-collector for electronic current and achieves shorter turn-off time.
1 citations
24 Oct 2000
TL;DR: In this article, the super-steep retrograde N-channel doping profile was found to degrade the gate oxide integrity (GOI), hot carrier lifetime and the ESD performance, and a modified LDD structure with As and P 31 co-implant followed by gate re-oxidation was also proposed to improve the hot-carrier lifetime.
Abstract: In this study, the super-steep retrograde N-channel doping profile was found to degrade the gate oxide integrity (GOI), hot carrier lifetime and the ESD performance. Therefore, a simple method was proposed to from the conventional -channel doping profile without adding the masking step. In addition, to improve the oxide/Si interface quality, a modified LDD structure with As and P 31 co-implant followed by gate re-oxidation was also proposed to improve the hot carrier lifetime. To improve the ESD failure threshold, after the real-time I-V characteristics measurement during ESD zapping event and detail failure analysis, a modified multi-finger protection structure with P+ diffusion into source regions was also proposed to relieve the current crowding effect. Moreover, for reducing the snapback voltage, a P- type dopant was proposed to implant into the drain region of the ESD transistor.
01 Jan 2015
TL;DR: This chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications, followed by a description of JFET types, basic operation,and characteristics and concludes with simple circuit applications of both transistors.
Abstract: Bipolar junction transistors (BJT) are inherent to CMOS technologies. Understanding the basic principles of operation of a BJT and its characteristics is not only important to efficiently use the component in Bipolar-CMOS (BiCMOS) applications. It is also important to understand bipolar effects in CMOS, such as subthreshold behavior, snapback, and latch-up, and to identify process and design techniques to modify their impact on circuit performance. Similarly, a discussion of integrated Junction field-effect transistors (JFET) is important to its use in analog designs, mainly as a very low-noise, high input-impedance device. It is also important to understand its parasitic effect, referred to as “The JFET Effect” in high-voltage, high power devices. The chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications. This is followed by a description of JFET types, basic operation, and characteristics. The chapter concludes with simple circuit applications of both transistors.