Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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Patent•
19 Jan 2021
TL;DR: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components can be integrated along a peripheral region of a high-voltage circuit such as a high side gate driver of a driver circuit as discussed by the authors.
Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.
Patent•
09 Jan 2018
TL;DR: In this paper, a leakage circuit containing a NMOS tube is arranged in an electrostatic protection circuit; the leakage circuit leaks the electrostatic voltage by using snapback conducting of the NMOS tubes.
Abstract: The invention belongs to the technical field of the electrostatic protection circuit, and specifically relates to an electrostatic protection circuit of the CLAMP type. A leakage circuit containing aNMOS tube is arranged in an electrostatic protection circuit; the leakage circuit leaks the electrostatic voltage by using snapback conducting of the NMOS tube; the working voltage of the NMOS tube islower than the electrostatic voltage, and the electrostatic protection circuit can simulate the running through simulation software, improves the success rate of the first current sheet, the financing cost and the time cost are saved.
01 Apr 2020
TL;DR: A 3.3V active ESD protection circuit is designed with a 16nm Fin-FET process through cascoding 1.8V FETs and validated by the fact that there is no sign of degradation in circuit-level behavior under realistic aging profiles.
Abstract: A 3.3V active ESD protection circuit is designed with a 16nm Fin-FET process through cascoding 1.8V FETs. The design is constrained by the lack of 3.3V FETs and the poor snapback characteristics of 1.8V FETs. The design is evaluated through circuit-level aging simulation to verify operational safety, and validated by the fact that there is no sign of degradation in circuit-level behavior under realistic aging profiles.
Patent•
04 May 2012
TL;DR: In this paper, a circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event.
Abstract: A circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event. The circuit includes at least one active device or capacitance-providing element connected to the gate of the protected MOS device, configured to pull down or hold down the voltage at the gate of the protected MOS device when the ESD event occurs.
01 Jan 2002
TL;DR: In this article, a no-snapback lateral double diffused MOSFET (LDMOSFet) was proposed for automotive applications under the condition of 15 kV, 150 pF, and 150, representing one order of magnitude higher ESD voltage than conventional LDMOS.
Abstract: This paper presents a no-snapback lateral double- diffused MOSFET (LDMOSFET), which endures the electrostatic discharge (ESD) requirement for automotive applications under the condition of 15 kV, 150 pF, and 150 , representing one order of magnitude higher ESD voltage than conventional LDMOS. First, the mixed (circuit and device) mode simulations analyze the typ- ical ESD failure dynamics of the conventional LDMOSFET, corre- lating the circuit level transient responses and the device level snap- back characteristics (i.e., the negative breakdown voltage-current ( ) characteristics). Then, the mechanism of the snapback is clarified from the aspect of the feedback link between the turn-on of the parasitic bipolar junction transistor (BJT) and the break- down of the drain n-n diode. Finally, a no-snapback LDMOSFET is experimentally demonstrated that attains the objective ESD en- durance.