Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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TL;DR: In this article , a snapback-free and fast-switching SOI LIGBT with three electron extracting channels (TEC) is proposed and investigated, which achieves the same breakdown voltage level of 603V as SBM without additional trench etch process required.
Abstract: In this paper, a snapback-free and fast-switching SOI LIGBT with three electron extracting channels (TEC) is proposed and investigated. Compared with SBM LIGBT, the trench gate of n-MOS is changed to a planar gate, and a P- region is added to prevent N+ short circuit while providing electron extracting channel. Simulation results show that TEC decreases EOFF by 15% at VON=1.8V relative to SBM when all three channels are open, while TEC still decreases EOFF by 10% at VON =1.55V relative to SBM when only two channels are available. The device achieves the same breakdown voltage level of 603V as SBM without additional trench etch process required.
TL;DR: In this paper , the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm bipolar-CMOS-DMOS (BCD) process were investigated.
Abstract: In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.
01 Jan 2023
TL;DR: In this article , the features and physics of snapback involved in 2D NMOS structures having body/substrate contact at bottom and adjacent to source under the application of high current ramp at drain and zero gate voltage.
Abstract: This paper compares the features and physics of snapback involved in 2D NMOS structures having body/substrate contact at bottom and adjacent to source under the application of high current ramp at drain and zero gate voltage. We analyzes the S-shaped current–voltage characteristics of two structures for understanding the snapback phenomenon and operational window of compact memory devices. This work also evaluates the carrier electrostatics involving the electron–hole carrier build up and ambipolar current flow in the body of the structures. We also investigate the formation of memory cell in the body of NMOS under zero gate bias and ramp of high current stress at drain terminal due to bipolar turn.
07 May 2008
TL;DR: Holding voltage adjustable Silicon Controlled Rectifier (HVASCR) as discussed by the authors is a SCR with possibility to tune the holding voltage, which forms good ESD (electrostatic discharge) protection.
Abstract: Holding voltage adjustable Silicon Controlled Rectifier (HVASCR) is a SCR with possibility to tune the holding voltage. The HVASCR structure forms good ESD (electrostatic discharge) protection. Such structures act as a protection of integrated circuits against parasitic electrostatic discharge. The use of such structures provides ICs robustness against ESD. Typical ESD cell is gate grounded NMOS transistor or SCR. The HVASCR enables tuning of I-V snapback characteristics. Simulated technology was CMOS very high voltage (VHVIC) and measurement was done for samples manufactured in 1.5 mum BiCMOS.
Patent•
12 Jan 2012TL;DR: An electrostatic discharge (ESD) protection circuit as discussed by the authors includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array with a different type of materials arranged in a second block.
Abstract: An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.