Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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TL;DR: In this paper, a no-snapback lateral double-diffused MOSFET (LDMOSFet) was proposed for automotive applications under the condition of 15 kV, 150 pF, and 150 /spl Omega/, representing one order of magnitude higher ESD voltage than conventional LDMOS.
Abstract: This paper presents a no-snapback lateral double-diffused MOSFET (LDMOSFET), which endures the electrostatic discharge (ESD) requirement for automotive applications under the condition of 15 kV, 150 pF, and 150 /spl Omega/, representing one order of magnitude higher ESD voltage than conventional LDMOS. First, the mixed (circuit and device) mode simulations analyze the typical ESD failure dynamics of the conventional LDMOSFET, correlating the circuit level transient responses and the device level snapback characteristics (i.e., the negative breakdown voltage-current (V-I) characteristics). Then, the mechanism of the snapback is clarified from the aspect of the feedback link between the turn-on of the parasitic bipolar junction transistor (BJT) and the breakdown of the drain n-n/sup +/ diode. Finally, a no-snapback LDMOSFET is experimentally demonstrated that attains the objective ESD endurance.
32 citations
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19 Jun 2013TL;DR: In this paper, a Snapback ESD protection device employing one or more nonplanar metal-oxide-semiconductor transistors (MOSFETs) is described.
Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.
32 citations
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27 Jan 1998TL;DR: In this paper, a series-connected semiconductor controlled rectifier and diode are electrically coupled between a pair of circuit nodes, and the diode can be utilized to increase a holding voltage between the pair of nodes.
Abstract: An ESD protection circuit of the present invention comprises a semiconductor controlled rectifier and at least one diode connected in series. The series-connected semiconductor controlled rectifier and diode are electrically coupled between a pair of circuit nodes. Even though the semiconductor controlled rectifier enters snapback during circuit operation the diode can be utilized to increase a holding voltage between the pair of circuit nodes. The required number of diodes is based upon the design consideration so that proper trigger voltage and holding voltage can be acquired. The semiconductor controlled rectifier can be a lateral semiconductor controlled rectifier, a low voltage triggering semiconductor controlled rectifier, or a floating-well semiconductor controlled rectifier.
32 citations
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TL;DR: In this article, a hybrid unipolar/bipolar operation with a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region.
Abstract: In this paper, ultrahigh-voltage (UHV) SiC devices with hybrid unipolar/bipolar operation are introduced and demonstrated. As the first step of such a device, a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region. A “snapback” phenomenon is intensively investigated by analytical modeling, device simulation, and experiment and a design guideline of snapback-free hybrid operating MPS diodes is presented. Using the design guideline, snapback-free MPS diodes are fabricated and forward characteristics are investigated. By using a proper edge termination structure, a UHV SiC MPS diode with breakdown voltage of 11.3 kV is demonstrated.
32 citations
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23 Mar 1999TL;DR: In this paper, the self-biased lateral NPN operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined, and the effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mm, and 0.25 /spl m/m.
Abstract: The self-biased lateral NPN (LNPN) operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined. The effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mu/m, and 0.25 /spl mu/m. Specifically, the influence of gate oxides <30 /spl Aring/, and the effects of CoSi/sub 2/ and TiSi/sub 2/ are characterized with the purpose of defining process dependencies and design space. It is shown that as gate oxides get thinner, oxide breakdown may become a limiting factor depending on the LNPN properties. Furthermore, changes in LNPN current gain through process or design variations, and the substrate resistance, can be used to tune ESD performance. Hence, transistor design and process choices can be made to ensure that the LNPN is optimized for successful operation even for very thin gate oxides in sub-0.2 /spl mu/m technologies.
31 citations