Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Programming of fuse-based memories using snapback devices

Abstract: In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.

Trade-off Characteristic between Gate Length Margin and Hot Carrier Lifetime by Considering ESD on NMOSFETs of Submicron Technology

Abstract: Hot carrier degradation and roll off characteristics of threshold voltage () on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control roll off down to the gate length margin. It was seen that the relationship between roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage () depends on drain current, and both and snapback holding voltage () depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

Snapback-free reverse conducting IGBT with p-float and n-ring surrounding trench-collector

Abstract: A reverse conducting (RC) insulated gate bipolar transistor (IGBT) with p-float and n-ring surrounding trench-collector is proposed. The p-floats surrounding sidewalls of trench-collectors suppress snapback and also avoid snapback when there are semiconductor/trench-collector interface charges (Q f). The n-rings surrounding the top of the trench-collectors speed up the forward recovery and ensure a high breakdown voltage. Technology computer aided design (TCAD) simulations are carried out to compare the proposed RC-IGBT and the RC-IGBT with p-poly trench-collector (PTC RC-IGBT). With Q f = 1 × 1011 cm−2, the proposed RC-IGBT is snapback-free while the PTC RC-IGBT has a snapback voltage of 4.43 V. The peak forward recovery voltage of the proposed RC-IGBT (12 V) is much lower than that of the PTC RC-IGBT (246 V). Besides, the reverse recovery charge of the two RC-IGBTs is 48% lower than that of the PiN diode.

Novel Layout Design of 4H-SiC Merged PiN Schottky Diodes Leading to Improved Surge Robustness

Abstract: In this work, a method to improve the surge current capability of silicon carbide (SiC) merged PiN Schottky (MPS) diodes is presented and investigated via three-dimensional electro-thermal simulations. When compared with conventional MPS diodes, the proposed structure has a more uniform current distribution during bipolar conduction due to the help of the continuous P+ surface, which can avoid the formation of local hot spots during the surge process. The Silvaco simulation results show that the proposed structure has a 20.29% higher surge capability and a 15.06% higher surge energy compared with conventional MPS diodes. The bipolar on-state voltage of the proposed structure is 4.69 V, which is 56.29% lower than that of conventional MPS diodes, enabling the device to enter the bipolar mode earlier during the surge process. Furthermore, the proposed structure can suppress the occurrence of “snapback” phenomena when switching from the unipolar the bipolar operation mode. In addition, the analysis of the surge process of MPS diodes is carried out in detail.

ESD-immunity Study of High-voltage nLDMOS with Vertical Parasitic Schottky Structures in the Source End

Abstract: In this paper, a TSMC $0.18- {\mu} \mathrm{m}$ BCD process is used to realize high-voltage n-LDMOS devices. And then, the source side $n^{{+}}$ layer of the reference device is removed, so that the source terminal will make a parasitic Schottky device. Next, in this paper, we will evaluate its impacts on the discharge current capability. There are four kinds of tested devices in this work, which are the reference, with whole source -Schottky MM, and removed half source electrode MN and maked half Schottky in source end NM type devices, respectively. According to the TLP testing results, three important values of snapback curve can be obtained: trigger voltage (${\mathrm{V}}_{{\mathrm t1}}$), holding voltage (${\mathrm{V}}_{{\mathrm{h}}}$), and secondary breakdown current (${\mathrm{I}}_{{\mathrm{t}}2}$). Finally, it can be concluded that if a Schottky device is added to the source terminal, the on-resistance will be increased due to the series connection of this Schottky device, then the trigger voltage can be increased about 2V and holding voltage increased about 8V.