Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Thermo-sensitive snapback behavioral model intended for electro-thermal simulation of power MOSFETs

Abstract: It is known that a second breakdown phenomenon similar to that observed in bipolar transistors can occur in power VDMOS, resulting from drain current snapback. A model for the drain current snapback phenomenon and its temperature dependence were investigated up to 300°C involving the avalanche multiplication of the channel current and the activation of the parasitic bipolar transistor. After presenting the theory, this model is compared with TLP (Transmission Line Pulsing) experimental results. Good agreement is achieved between calculated and measured boundaries of the current before and after the snapback has occurred.

Esd protection circuit for an integrated circuit with a negative voltage input terminal

Abstract: An ESD protection circuit is provided for protecting an integrated circuit from ESD damage and for protecting lightening surge. The ESD protection circuit includes a first snapback device and a second snapback device. The first snapback device is connected to a first terminal having a negative voltage of the integrated circuit during the operation of the integrated circuit. The first snapback device includes an anode coupled to the first terminal of the integrated circuit. The cathode of the first snapback device is coupled to a VCC terminal of the integrated circuit. The second snapback device has a cathode coupled to the VCC terminal. The anode of the second snapback device is connected to the ground of the integrated circuit. The snapback devices operate as silicon-controlled rectifiers (SCR) to protect the integrated circuit.

CMOS ESD clamp with input and separate output voltage terminal for ESD protection

Abstract: In a snapback NMOS ESD protection structure, the output voltage presented to an internal circuit for ESD protection is limited by providing for a separate output terminal at a lower voltage than the input terminal. The voltage drop between the two terminals is achieved by connecting the input and output terminals to different parts of a ballast region of the structure and using the saturation resistance of the portion of the ballast region between the terminals to achieve the voltage drop.

Programmable ESD protection structure

Abstract: In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.

Horizontal RC-IGBT device with surface dual-gate control

Abstract: The invention discloses a horizontal RC-IGBT device with surface dual-gate control, and belongs to the technical field of a power semiconductor. According to the device, a fly-wheel diode with a conventional structure is connected with a MOS transistor in series; the starting and closing of the MOS transistor is controlled through a second gate, so as to realize the functions which are the same as those of the conventional structure; when the RC-IGBT is in forward operation, the MOS transistor is closed, an N+ collector region in the conventional structure is isolated by the MOS transistor, and at the moment, the device is equivalent to be a pure IGBT, so that a voltage snapback phenomenon in the conventional structure is completely eliminated; when the device is in backward operation, the starting of the MOS transistor is controlled by the second gate, and the fly-wheel diode can work as normal; meanwhile, different from the conventional device with the longitudinal structure, the device disclosed in the invention is the transverse device, the device is established on an epitaxial layer, and a back surface process is not needed for realization of the device, so that the technological difficulty is greatly lowered; and through an RESURF structure, the transverse voltage withstand performance of the device is also reinforced.