Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
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TL;DR: In this article , a 4H-SiC IGBT with a multifunctional P-floating layer (MP-IGBT) is proposed and investigated by Silvaco TCAD simulations.
Abstract: In this paper, a 4H–SiC IGBT with a multifunctional P-floating layer (MP-IGBT) is proposed and investigated by Silvaco TCAD simulations. Compared with the conventional 4H–SiC field stop IGBT (FS-IGBT), the MP-IGBT structure features a P-floating layer structure under the N-buffer layer. The P-floating layer increases the distributed path resistance below the buffer layer to eliminate the snapback phenomenon. In addition, the P-floating layer acts as an amplifying stage for the hole currents’ injection. The snapback-free structure features a half-cell pitch of 10 μm. For the same forward voltage drop, the turn-off loss of the MP-IGBT structure is reduced by 42%.
29 Nov 2020
TL;DR: In this paper, the authors proposed a strategy of suppressing the snapback effect by optimizing the backside layout of devices and point out that increasing the equivalent resistance of collector is the critical solution.
Abstract: The snapback effect of RC-IGBT occurs when the device transits from the unipolar mode to the bipolar mode during the turn-on process, which will increase the switching loss and affect the reliability of the device. In this paper, we analyze the turn-on process of RC-IGBT and build the mathematical physic model of the lateral-flowing electron current by using the infinitesimal method. We come up with a strategy of suppressing the snapback effect by optimizing the backside layout of devices and point out that increasing the equivalent resistance of collector is the critical solution. There are several specific methods of operation, such as increasing the number of MOS cells in parallel, decreasing the length of N+ short properly or optimizing the relative position of N+ short. By using Silvaco TCAD simulation software and combining the semiconductor fabrication process, we achieve the snapback-free I-V characteristic of RC-IGBT devices, which verifies the availability of our proposed suppression strategy. This research provides a significant reference for the design of RC-IGBT.
TL;DR: In this paper, the authors presented an ESD robustness enhancement study of an 800 V junction field effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure.
Abstract: Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure.
Patent•
04 Jan 2017
TL;DR: In this article, a gate-grounded N-channel metal Oxide Semiconductor (GGNMOS) was applied to ESD (Electro-Static discharge) protection and a manufacturing method thereof.
Abstract: The invention discloses a GGNMOS (Gate-Grounded N-channel Metal Oxide Semiconductor) device applied to ESD (Electro-Static discharge) protection and a manufacturing method thereof. A P-type doping region is arranged in a drain extension region of a GGNMOS to form a floating reverse diode with a drain NLDD (N-type Lightly Doped Drain) doping region, so that distribution of drain ESD current is changed; ESD leakage current is deviated from the surface of the drain extension region and a conducting channel; the cooling capability during ESD discharge of the GGNMOS is enhanced; secondary breakdown current during snapback of the device is increased; and the ESD protection capability of the GGNMOS device is enhanced.
TL;DR: In this paper , the authors presented a 1200V-class reverse conducting insulated gate bipolar transistor (RC-IGBT) with low switching energy consumption, which was designed in accordance with the latest enhanced trench and field stop technology while incorporating an anti-parallel Free Wheeling Diode (FWD) between the adjacent FS-IBT cells.
Abstract: This paper presents a 1200V-class reverse conducting insulated gate bipolar transistor (RC-IGBT) with low switching energy consumption (LE-RC-IGBT). Its structure was designed in accordance with the latest enhanced trench and field stop technology while incorporating an anti-parallel Free Wheeling Diode (FWD) between the adjacent FS-IGBT cells. With the Emitter Shorted Diode (ESD) technology employed in the design of the FWD structure, the FWD and FS-IGBT can be made simultaneously. By using the same trench etching technique of the gate process, oxide trench was formed on the back side of the device to increase the short-circuit resistance between the N+ Collector and the P+ Collector on the back of the RC-IGBT. The voltage snapback phenomenon of the conventional RC-IGBT was completely eliminated. The electrical characteristics of the RC-IGBT were investigated by using Sentaurus-TCAD. Simulation results show that the switching energy consumption of the proposed LE-RC-IGBT is reduced by approximately 50%compared with the conventional one.