Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Electro-static discharge protection device having a modulated control input terminal

Abstract: A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.

Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 /spl mu/m CMOS technology

Abstract: An electrostatic discharge (ESD) evaluation of a silicided 0.25 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology is carried out by HEM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Internal ESD protection circuit for semiconductor devices

Abstract: An internal electrostatic discharge (ESD) protection circuit for semiconductor devices defines a structure for protecting adjacent n-channel devices. The first n-channel device includes a pair of n+ regions defining source and drain regions wherein the drain region is connected to a positive power supply terminal (VDD). The second, adjacent, n-channel device also includes a pair of n+ regions forming source and drain regions, respectively, wherein the source region of the second n-channel device is connected to a negative power supply terminal (VSS). The drain of the first n-channel device is laterally spaced, and isolated from the source of the second n-channel device by a thick field oxide region. The novel structure includes forming an N-conductivity type well that substantially overlaps the drain n+ region of the first n-channel device and extends toward the n+ region that forms the source of the second n-channel device. The N-well is doped to a lower density than the n+ regions, and further, is formed into the substrate to a depth that is substantially larger than the depth of the n+ regions. The N-well substantially increases the junction breakdown voltage of the device. Alternately, a p+ conductivity guard ring is disposed intermediate the n+ region forming the drain of the first n-channel device, and the n+ region forming the source of the second n-channel device to thereby reduce the current gain of a parasitic NPN bipolar transistor formed between the two n-channel devices. The decreased current gain prevents snapback triggered by an ESD event.

Reverse conducting–IGBTs initial snapback phenomenon and its analytical modelling

Abstract: Analytical models have been proposed to describe the onset current density for the initial snapback in the transistor on-state mode and in the blocking state of reverse conducting-insulated gate bipolar transistors (RC-IGBT) for the stripe and cylindrical designs of the anode shorts. In cylindrical case, there are two possible ways in designing the anode shorts and the authors have proposed an analytical model for each of them. The considered RC-IGBTs are vertical with soft punch-through type buffer designs. The analytical model has been evaluated with the aid of 2-D device simulations and measurements. The authors have investigated the initial snapback phenomenon for different voltage class devices at a given technology (anode and buffer profiles) and found out that the snapback voltage increases with the blocking capability but not the snapback current density. The authors have also observed that the initial snapback phenomenon is more pronounced at lower temperatures. From the analytical model as well as simulation and measurement results, the authors have found that for a given voltage class and technology, the p + -anode width is the only remaining design degree of freedom which determines the initial snapback. The adjustment of the on-state losses can then be done with the proportion of the n + -short region.

Pfet-based esd protection strategy for improved external latch-up robustness

Abstract: A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.