Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Toward Stronger Robustness of Network Controllability: A Snapback Network Model

Abstract: A new complex network model, called ${q}$ -snapback network, is introduced. Basic topological characteristics of the network, such as degree distribution, average path length, clustering coefficient, and Pearson correlation coefficient, are evaluated. The typical 4-motifs of the network are simulated. The robustness of both state and structural controllabilities of the network against targeted and random node- and edge-removal attacks, with comparisons to the multiplex congruence network and the generic scale-free network, are presented. It is shown that the ${q}$ -snapback network has the strongest robustness of controllabilities due to its advantageous inherent structure with many chain and loop motifs.

ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Abstract: This paper presents an ESD protection design scheme for mixed-power domains in narrow ESD design window with ultra-thin gate oxides. Using a grounded gate (gg)NMOS-based clamp with contact ballast (CTB) layout technique, a factor of 3X area reduction can be achieved for MM protection of a 1.6 nm gate oxide compared to a conventional silicide-block ESD scheme. To expand the design window, a novel ground current trigger (GCT) technique using current sensing circuit between different GND busses is proposed. 7 kV HBM and 550 V MM can be achieved with a 2nd clamp with GCT technique, with the same area as a conventional snapback protection device. The GCT technique is also effective for SCR trigger element as cross clamp.

An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

Abstract: In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 /spl mu/m, 35 /spl Aring//70 /spl Aring/ dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over nonSI and SI I/O pad designs, respectively.

Analysis and design of the dual-gate inversion layer emitter transistor

Abstract: The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.

High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.