Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

ESD Scalability of LDMOS Devices for Self-Protected Output Drivers

Abstract: Lateral DMOS (LDMOS) power transistors of SMART technologies are widely used as output drivers in multiple applications. However, LDMOS devices are generally not robust under ESD due to deep snapback causing localized current crowding and leading to inhomogeneous triggering of the parasitic bipolar, ESD ruggedness of LDMOS power devices has been a significant subject in smart power IC technology. Lack of understanding in geometry scalability of the LDMOS devices often thwarts a proper implementation of self-protected structures. Therefore, it is necessary to understand the ESD scalability and failure mechanism of the power output devices to meet various levels of design requirement and optimize ESD protection solution. LDMOS devices ESD capability has been understood from snapback breakdown of the parasitic bipolar components. They usually show different behavior under ESD stress conditions, compared to the normal MOS transistors. The triggering mechanism of the snapback breakdown has been major subjects in terms of device structures and designs. In this paper, we report an ESD capability and scalability of the LDMOS devices from the geometry and operational aspects, employing both experimental and simulation data. Difference of transient electrical behaviors and failure mechanisms of DMOS with different geometries under ESD stress conditions is also addressed

Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool

Abstract: The purpose of this work is to present a new phenomenon in the ElectroStatic Discharge (ESD) failure threshold of deep submicron CMOS technologies. Although the bipolar conduction mode (or snapback) used for the protection was considered as uniform, we present dynamic EMission MIcroscopy (EMMI) studies showing for the first time that the current does not instantly spread out over the complete width of the transistor. Furthermore, this phenomenon leads to a saturation of failure threshold for the widest transistors and plays a major part in the failure threshold of devices. Different parameters having an influence on the spreading of the current are analyzed and interesting conclusions for the design of ESD hard NMOS devices are drawn.

Reverse-conducting insulated gate bipolar transistor with an anti-parallel thyristor

Abstract: An IGBT with a novel reverse conduction structure is presented and first demonstrated by numerical simulations. As opposed to the standard anti-parallel diode existent in power MOSFETs and conventional reverse conducting IGBTs, here we propose an anti-parallel reverse-conducting thyristor with a very low break-over voltage. The structure includes a narrow-base npn BJT to realise an embedded thyristor which acts like a diode in its on-state conduction. In addition, the narrow-base npn BJT helps to mitigate the snapback issue which usually appears in the conventional RC-IGBTs. The new device also feature a number of floating N+ dots in the N-buffer layer to adjust the device static and switching performance without the need of cumbersome lifetime killing processes. Simulation results have shown that the new device can achieve a low on-state voltage of 1.3 V in forward conduction and 1.2 V in reverse conduction, for 600-V blocking rating, coupled with fast switching performance.

Esd protection circuit

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit therebetween Under a normal operating condition, a voltage on the first pad is higher than that on the second pad The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring

Compact electro‐thermal simulation of ESD‐protection elements

Abstract: Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro-thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD-hardness and HBM-failure thresholds of protection structures.