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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


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Patent
11 Dec 2002
TL;DR: In this article, a pin-to-pin electrostatic discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain.
Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

20 citations

Patent
01 Mar 1999
TL;DR: In this paper, an ESD protection circuit which may be implemented in thin epitaxial substrate surfaces was proposed. But the circuit was not implemented in a trench isolated area of the substrate.
Abstract: An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.

19 citations

Proceedings ArticleDOI
17 Apr 2016
TL;DR: In this article, the effect of MESA isolation and gate finger on the ESD behavior of AlGaN/GaN HEMTs was analyzed and a unique power law like behavior was found.
Abstract: Present experimental study reports various failure modes under ESD stress conditions and distinct ESD behavior of AlGaN/GaN HEMTs for the first time. Effect of MESA isolation and gate finger on the ESD behavior of HEMTs is analyzed. Effect of pulse width on ESD robustness and snapback voltage is observed and a unique power law like behavior is found. Cumulative nature of device degradation under ESD stress condition is discovered. Correlation between depth of snapback and failure threshold with % device degradation is found. Finally, impact of inverse piezoelectric effect in AlGaN/GaN system, fringing electric field, role of contact resistivity, temperature and field induced contact metal migration and premature breakdown of parasitic MESA Schottky junction are studied in context to AlGaN/GaN HEMT failure ESD conditions.

19 citations

Patent
25 Nov 1996
TL;DR: In this paper, a low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of IC from ESD damage using at least one NMOS transistor and at least two SCR connected in parallel between the binding pad and a circuit ground point.
Abstract: A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 μm 2 smaller than that of prior art for space saving. For more precise statement, the invention provides about 10% chip area saving.

19 citations

Journal ArticleDOI
TL;DR: In this article, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event was investigated by using a real-time current and voltage measurement, which revealed the existence of ldquoself-consistent effect, i.e., the turnon region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current.
Abstract: In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of ldquoself-consistent effect,rdquo i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (ID). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with ID instead of 0.6-0.8 V and independent of ID as reported in early literatures.

19 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824