Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Decay and snapback in superconducting accelerator magnets

Abstract: This thesis deals with the explanation and compensation of the effects ‘decay’ and ‘snapback’ in superconducting accelerator magnets, in particular in those used in the new Large Hardron Collider at CERN. During periods of constant magnet excitation, as for example during the injection of particles in the storage ring, the magnetic field in superconducting accelerator magnets shows a decay behavior. As soon as the particles are accelerated, the magnets are ramped, and the magnetic field ‘snaps back’ to the original hysteresis curve. Decay and snapback affect the beam in the machine and have to be compensated precisely in order to avoid losses of particles.

An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

Abstract: A new silicon-controlled rectifier (SCR) is proposed and realized in a 0.35-mum/3.3-V fully salicided BiCMOS process for electrostatic-discharge (ESD) applications. Without using an external trigger circuitry, the unassisted SCR has a trigger voltage as low as 7 V to effectively protect deep-submicrometer MOS circuits, a holding voltage higher than the supply voltage to minimize transient influence and avoid latch-up issue, and a second snapback current density exceeding 60 mA/mum to provide robust ESD-protection solutions.

High voltage ESD-protection structure

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, eg, diode, in the ESD protection structure Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, eg, transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (eg, diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value) The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit

Modeling of output snapback characteristics in n-channel SOI MOSFETs

Abstract: The snapback effect is usually observed in the output characteristics of an n-channel SOI MOSFET with zero gate voltage in which the drain-to-source breakdown voltage is less than the drain-to-body avalanche voltage. It can be attributed to parasitic lateral bipolar actions as well as the MOS feedback mode of operation-a point often overlooked in the literature. An analytical model is developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms. Results obtained from this model agree well with the experimental I-V curves, and show that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future. >

Dynamic substrate-coupled electrostatic discharging protection circuit

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source V DD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.