Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

A double RESURF LDMOS with drain profile engineering for improved ESD robustness

Abstract: This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA//spl mu/m has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size.

ESD protection for deep submicron CMOS devices with minimum tradeoff for latchup behavior

Abstract: Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well. The triggering voltage for snapback of the SCR device is tunable over a voltage range as low as 5-11 Volts, and the device dynamical resistance in the on-state is about 8-9 Ohms. The SCR device has reduced tradeoff with latchup behavior of the electronic device to be protected.

Snapback and safe operating area of LDMOS transistors

Abstract: This paper deals with the measurement and prediction of the SOA boundary and the accompanying device physics. Results are given for n-channel LDMOS transistors having a self-aligned body diffusion. LDMOS SOA has been discussed previously in a number of papers, however, there is still a need for improving the overall understanding of this rather complicated subject. To be complete, thermal effects should also be included in the definition of SOA, however, these can be treated separately and we focus here on the "electrical SOA", which is defined by the Id-Vds boundary where snapback occurs.

Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

Abstract: We present the underlying mechanisms of second breakdown in deep submicron nMOS transistors under high current snapback conditions The onset of second breakdown is shown to be determined by a rapid increase in the thermally generated component of the substrate (base) current Simplified simulation methodologies for evaluating high current robustness using isothermal device simulations are demonstrated and good correlations with experimental data have been obtained >

Low capacitance ESD protection device

Abstract: An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion) is located on either side of each source (N+ diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.