Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Tile-level snapback detection through coupling capacitor in a cross point array

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.

Co-design methodology to provide high ESD protection levels in the advanced RF circuits

Abstract: This paper describes an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends. The RF constraints on the ESD devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize. The method is applied to the design of 0.25 mum CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional high capacitive ggNMOS snapback devices.

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Abstract: In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mum 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.

Apparatuses, devices and methods for sensing a snapback event in a circuit

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Physical limitation of the cascoded snapback NMOS ESD protection capability due to the non-uniform turn-off

Abstract: The nonlinear effects and physical failure mechanism in over-voltage protection NMOS snapback structures during ESD operation have been analyzed with the use of experimental test structures as well as process and device simulations. A phenomenological explanation has been provided to account for the effect due to substrate type and the use of a so-called ESD implant. A generic design solution for the cascoded snapback NMOS structure suitable for 5-V tolerant I/O applications is proposed, one that delivers robust operation and eliminates the requirement for an additional ESD implant.