Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Novel Silicon-Controlled Rectifier With Snapback-Free Performance for High-Voltage and Robust ESD Protection

Abstract: A novel snapback-free silicon-controlled rectifier (SFSCR) with P-type Zener implantation (ZP) is developed in a 0.5- $\mu \text{m}$ bipolar CMOS DMOS technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a serious degradation in failure current ( ${I}_{\textsf {t2}}$ ) when compared with the regular low holding voltage ( ${V}_{h}$ ) device. In order to mitigate such degradation, a novel layout terminal is proposed. According to the transmission-line pulse test results, ${I}_{\textsf {t2}}$ of the SFSCR with new layout is increased by 58.5%, while the ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) is reduced by 48.7% under the same layout area. By comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution.

Distinct Failure Modes of AlGaN/GaN HEMTs Under ESD Conditions

Abstract: This article reports the distinct failure mechanisms and insights on device degradation of AlGaN/GaN high electron mobility transistors (HEMTs) under electrostatic discharge (ESD) stress conditions. The role of device surface, MESA isolation, and gate Schottky junction in defining the degradation type is discovered. Premature breakdown at the MESA Schottky junction and dislocation induced failure in the active region and their consequences on ESD robustness are reported. Physical mechanisms responsible for snapback instability in transmission line pulsing (TLP) characteristics are discussed. Change in device failure from soft to hard with pulsewidth is revealed. Finally, the role of contact resistivity, surface diffusion, and channel electric field and its fringing effect at contacts are analyzed in context to ESD failure of AlGaN/GaN HEMTs. Various stages of device degradation during TLP stress are captured on-the-fly using high-resolution (HR) optical microscopy and high-speed Si charge-coupled device (CCD) detector. Postdevice failure, damaged regions are analyzed using transmission electron microscopy and scanning electron microscopy together with in situ energy-dispersive X-ray spectroscopy to probe details of failure mechanisms involved. Finally, based on the learning from this article, design guidelines for an ESD robust HEMT are proposed.

Method and system for extracting high current parasitic bipolar transistor parameters of an MOS device during overvoltage events

Abstract: An embodiment of the instant invention is a method of optimizing an I/O circuit formed on a substrate with regards to an overvoltage or ESD event wherein the I/O circuit comprises at least one MOS device which has I-V characteristics, the method comprising the steps of: extracting selective electrical characteristics of the MOS device while the MOS device is operating in the avalanche and snapback regions of the I-V characteristics of the MOS device; characterizing the MOS device for the overvoltage or ESD event based on the electrical characteristics of the MOS device under standard operating conditions, the MOS device being comprised of a parasitic bipolar transistor and the substrate having a resistance; and wherein the I/O circuit is optimized for the overvoltage or ESD events by modifying the I/O circuit based on the electrical characteristics of the MOS device in conjunction with the characterization of the parasitic bipolar transistor and the substrate resistance.

A snapback suppressed reverse-conducting IGBT with uniform temperature distribution

Abstract: A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. Moreover, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.