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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


Papers
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Patent
12 Jun 2006
TL;DR: In this article, a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly-layer segmentation to segment the source or drain area.
Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

11 citations

Patent
08 Jan 2009
TL;DR: In this paper, a control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage.
Abstract: Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

11 citations

Journal ArticleDOI
TL;DR: New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed and it is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions.

11 citations

Journal ArticleDOI
TL;DR: In this paper, the impact of the base-pushout or Kirk-effect on the ESD characteristic of modern radio frequency (RF) NPN transistors is investigated, and concepts to exploit the base pushout effect for improved RF protection schemes are presented.

11 citations

Journal ArticleDOI
TL;DR: Characteristics of electrostatic discharge protection devices operating under various ambient temperatures are investigated including Lateral SCR and P-Substrate Triggered SCR fabricated in a 0.35 um BCD (Bipolar-CMOS-DMOS) technology.

11 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824