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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


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Journal ArticleDOI
TL;DR: In this paper, a system based on Hall probes was developed from an existing prototype to measure with a moderate acquisition frequency (3-10 Hz) the decay and snapback of the sextupole and decapole fields.
Abstract: During beam injection the components of the magnetic field inside the magnets decay in time. At the re-start of the ramping, this decay is cancelled resulting in a fast change of the harmonics called "snapback". This sudden variation affects mainly the sextupole and decapole components and can induce significant changes in the machine chromaticity, thus causing particle beam loss. Standard magnetic measurements with rotating coils do not have a sufficient time resolution to properly characterize the snapback phenomenon. A system based on Hall probes has been developed from an existing prototype to measure with a moderate acquisition frequency (3-10 Hz) the decay and snapback of the sextupole and, for the first time, of the decapole fields. The present system also provides local measurements of these field harmonics along a wavelength of the superconducting cable twist pitch. In this paper, we describe the assembly features of this detector and of the measurement chain. The performances are demonstrated based on preliminary measurements performed on the LHC pre-series dipoles in operating conditions.

11 citations

Patent
03 Dec 2015
TL;DR: In this article, a non-snapback device and a snapback device are coupled between either an I/O pad or a power pad and a ground terminal, and the voltage across the two devices is held at the same holding voltage.
Abstract: An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.

11 citations

Proceedings ArticleDOI
16 May 2005
TL;DR: In this paper, a new correction algorithm was proposed to compensate for the decay of the sextupole field during the dwell at injection and for the subsequent field "snapback" during the first few seconds of the energy ramp.
Abstract: Since the beginning of 2002 an intensive measurement program has been performed at the Fermilab Magnet Test Facility (MTF) to understand dynamic effects in Tevatron magnets. Based on the results of this program a new correction algorithm was proposed to compensate for the decay of the sextupole field during the dwell at injection and for the subsequent field "snapback" during the first few seconds of the energy ramp. Beam studies showed that the new correction algorithm works better than the original one, and improves the Tevatron efficiency by at least 3%. The beam studies also indicated insufficient correction during the first 6s of the injection plateau where an unexpected discrepancy of 0.15 sextupole units of extra drift was observed. This paper reports on the most recent measurements of the Tevatron dipoles field at the beginning of the injection plateau. Results on the field decay and snapback in the Tevatron quadrupoles are also presented.

11 citations

Journal ArticleDOI
TL;DR: In this paper, an n-MOSFET (MN2) is embedded in the anode side of the LIGBT to short the P-anode/N-buffer junction during the turn-off transient, thus allowing the LigBT to be turned off rapidly without excessive tail current.
Abstract: A novel snapback-free and low turn-off loss reverse-conducting (RC) SOI-LIGBT is proposed and investigated by numerical simulations. An n-MOSFET (MN2) is embedded in the anode side of the LIGBT to short the P-anode/N-buffer junction during the turn-off transient, thus allowing the LIGBT to be turned off rapidly without excessive tail current. In addition, MN2 enable the LIGBT to conduct the reverse conducting current like the freewheeling diode. In the forward-conducting state, MN2 is turned off, then the proposed LIGBT operates like a conventional one and the snap-back is avoided. The gate electrode of MN2 can be controlled synchronously by the gate signal of the LIGBT which is level-shifted by a p-i-n diode (D1) and processed by an anode-controlling circuit, and therefore, the proposed RC-LIGBT still maintains a three-terminal configuration. D1 and MN2 are embedded in the drift region and anode-side of the LIGBT, respectively, and they can be isolated by deep-oxide trenches. The numerical simulation results reveal that the turn-off loss ( ${E} _{\mathrm{ off}}$ ) and reverse recovery charge of the proposed LIGBT is reduced by 58.3% and 38.9%, respectively, compared with the conventional LIGBT combining with antiparallel freewheeling diode.

11 citations

Proceedings ArticleDOI
01 May 2017
TL;DR: In this article, a self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented, where a parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDM OS to operate within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown.
Abstract: A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.

10 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824