Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Novel high voltage ESD protection device with very low snapback voltage

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+ diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+ diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Overcurrent protection for an ink-jet printhead

Abstract: A protection circuit prevents snapback events in MOS transistors associated with semiconductor or micromechanical structures, such as ink-jet ejectors. A bulk electrode associated with the MOS transistor is monitored for unusual high voltages which are consistent with an impending snapback event. The voltage on the bulk electrode is then used to turn on the control transistor which connects the gate of the MOS transistor to ground and thereby protects the device.

ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V ss ) and/or V cc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n + -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n + source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Electrostatic discharge protection device for mixed voltage application

Abstract: A novel electrostatic discharge (ESD) protection device used for mixed voltage application is disclosed. A primary ESD device and a MOS transistor stack are respectively coupled to the input/output pad. The MOS transistor stack is formed in a cascode configuration comprising a first MOS transistor and a second MOS transistor form in different active areas. The drain region of the first MOS transistor is coupled to the input/output pad and the gate region is coupled to a low power supply. The second drain region of the second MOS transistor is coupled to the source region of the first MOS transistor, while the gate region and the source region grounded. The primary ESD device is selected with a junction breakdown voltage no more than the lowest junction breakdown voltage of the MOS transistor stack, so that the primary ESD device enters snapback prior to the MOS transistor stack.

MOSFET flyback-diode conduction and dV/dt effects in power ICs in low-voltage motor control applications

Abstract: In a power IC, the direct drive of a low-voltage motor by one or more MOSFET half-bridges results in inductive-flyback diode conduction during switching transitions. PISCES computer simulation reveals that this diode current in an integrated lateral MOSFET manifests itself as parasitic bipolar conduction where a substantial fraction of the carriers injected from the forward-biased drain-to-body junction is collected by the transistor's source. The physics of parasitic bipolar turn-off, or recovery, is shown to depend on the application. The resulting driving-point conditions can be classified into one of three possible diode recovery scenarios. In either natural or synchronously clamped recovery, high dV/dt is prevented by the inductive time constant of the motor. In forced recovery operation, fast diode turn-off and high dV/dt results from shoot-through between the recovering diode and the MOSFET within a given half-bridge. analysis reveals that a high dV/dt leading to minority carrier injection from the source slows the forced reverse-recovery time without leading to destructive snapback. >