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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


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Patent
04 Aug 2003
TL;DR: A memory may have access devices formed using a chalcogenide material The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed as mentioned in this paper.
Abstract: A memory may have access devices formed using a chalcogenide material The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element

56 citations

Journal ArticleDOI
TL;DR: In this article, a high-voltage SCR stacking structure with an extremely high holding voltage, very small snapback, and acceptable failure current has been developed for high voltage ESD protection.
Abstract: Latchup immunity is a challenging issue for the design of power supply clamps used in high-voltage electrostatic discharge (ESD) protection applications. While silicon-controlled rectifiers (SCRs) are highly robust ESD devices, they are traditionally not suited for high-voltage ESD due to their inherent low holding voltage and, thus, vulnerability to latchup. In this letter, a novel SCR stacking structure with an extremely high holding voltage, very small snapback, and acceptable failure current has been developed. The new and existing high holding voltage ESD devices are also compared to demonstrate the advancement of this work.

56 citations

Proceedings ArticleDOI
01 Jan 1998
TL;DR: In this article, the triggering of grounded gate nMOSFET and field-oxide devices (FOXFETs) is addressed by TLP-pulsed emission microscopy.
Abstract: The triggering of grounded gate nMOSFET (gg-nMOS) and field-oxide devices (FOXFETs), essential for optimized ESD protection design, is addressed by TLP-pulsed emission microscopy. Current nonuniformity and instability effects in snapback operation under DC and TLP conditions are demonstrated. The comprehensive correlation of emission and electrical behaviour allows an improved interpretation of device operation. Technological influences on the trigger uniformity are discussed.

56 citations

Patent
16 Dec 2002
TL;DR: In this paper, a gate-coupled MOSFET ESD protection circuit was proposed, where a pulldown element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event.
Abstract: A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.

54 citations

Journal ArticleDOI
Steven H. Voldman1, Vaughn P. Gross1
TL;DR: In this article, the effect of scaling on electrostatic discharge (ESD) robustness in 1.2 to 0.25 μm channel length CMOS technologies is explored for ESD protection circuits and MOSFET structures.

53 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824