scispace - formally typeset
Search or ask a question
Topic

Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


Papers
More filters
Proceedings Article
01 Jan 2012

9 citations

Journal ArticleDOI
TL;DR: In this article, the parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress, and the optimal gate length for CDM protection in advanced submicron technologies is discussed.

9 citations

19 Sep 2000
TL;DR: In this paper, the authors used the Sandia nuclear microprobe to create charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths and showed that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity.
Abstract: Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an interesting saturation effect of SES versus the amount of injected charge is observed.

9 citations

Proceedings ArticleDOI
11 Jul 2016
TL;DR: In this article, the authors investigated the impact of MOS device physical dimensions on grounded-gate N-channel MOS (GNMOS) transistor's ESD protection.
Abstract: MOS (Metal-Oxide-Semiconductor) transistor is widely used as ESD (Electro-Static Discharge) protection because of its good snapback characteristics. GGNMOS (Grounded-Gate N-channel MOS) has the advantage of simple construction, easy triggering and low power dissipation, also has the self-ability of ESD protection. The thesis researches in deep sub-micron CMOS (Complementary MOS) technology and MOS device physical dimensions impacting on GGNMOS's ESD characteristics. And the conclusion provide evidence for the device layout design.

9 citations

Journal ArticleDOI
TL;DR: In this article, the authors compared reoxidized nitrided oxides (RNOs) with conventional oxides with respect to their susceptibility to latent damage from electrostatic discharge (ESD) and ESD-like events.
Abstract: n-channel MOSFETs with reoxidized nitrided oxides (RNOs) are compared to conventional oxides with respect to their susceptibility to latent damage from electrostatic discharge (ESD) and ESD-like events. It is shown, using both ESD events and simulated ESD events by snapback, that the RNO devices have substantially better resistance to latent damage from such events. The increased resistance is explained by the robustness of the nitrided oxides both to interface state generation and to oxide trap creation by hot-hole injection. It is concluded that, along with hot-carrier resistance, the RNO robustness to latent ESD damage is another advantage of this technology. >

9 citations


Network Information
Related Topics (5)
Transistor
138K papers, 1.4M citations
86% related
CMOS
81.3K papers, 1.1M citations
85% related
Integrated circuit
82.7K papers, 1M citations
84% related
Field-effect transistor
56.7K papers, 1M citations
83% related
Capacitance
69.6K papers, 1M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824