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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


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Patent
01 Sep 2009
TL;DR: In this article, an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) that provides ESD protection during an ESD event is disclosed, which includes a first EDS protection component coupled in series to the second EDS component.
Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) that provides ESD protection during an ESD event is disclosed. The electrostatic discharge (ESD) protection circuit includes a first electrostatic discharge (ESD) protection component and a second electrostatic discharge (ESD) protection component coupled in series to the first electrostatic discharge (ESD) protection component. A snapback holding voltage of the electrostatic discharge protection circuit is greater than the operating voltage of the electrostatic discharge protection circuit and a snapback trigger voltage of the electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said integrated circuit.

9 citations

Patent
31 Oct 2002
TL;DR: In this paper, a combination of a current limiting resistor and a clamping Schottky diode was used to prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event.
Abstract: A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event. Minority carrier injection from n+ devices is substantially reduced, and the circuit may also be used to clamp an oxide voltage in a thin oxide semiconductor device.

9 citations

Journal ArticleDOI
TL;DR: In this paper, a simple and compact model for the n-well resistor is derived specifically for use in simulation and design of ESD protection circuits using SPICE, which encompasses three regions of resistor operation: linear and velocity saturation, avalanche multiplication and snapback and high injection.
Abstract: A simple and compact model is derived for the n-well resistor. The model was derived specifically for use in simulation and design of ESD protection circuits using SPICE. Hence it encompasses three regions of resistor operation: linear and velocity saturation, avalanche multiplication and snapback and high injection. Excellent fit with experimental data is found.

9 citations

Journal ArticleDOI
06 Feb 2007-Chaos
TL;DR: It is shown how analysis from numerical computation of orbits can be applied to prove the existence of snapback repellers in discrete dynamical systems.
Abstract: In this paper we show how analysis from numerical computation of orbits can be applied to prove the existence of snapback repellers in discrete dynamical systems. That is, we present a computer-assisted method to prove the existence of a snapback repeller of a specific map. The existence of a snapback repeller of a dynamical system implies that it has chaotic behavior [F. R. Marotto, J. Math. Anal. Appl. 63, 199 (1978)]. The method is applied to the logistic map and the discrete predator-prey system.

9 citations

Journal ArticleDOI
TL;DR: In this paper, the authors used TCAD (technology computer-aided design) to calculate practical NMOS and PMOS device behaviors under ESD/EOS events, including electrothermal effect with lattice temperature parameters.
Abstract: This paper uses TCAD (technology computer-aided design) to calculate practical NMOS and PMOS device behaviors under ESD/EOS events The simulations include electrothermal effect with lattice temperature parameters These simulations reproduce TLPG (transmission line pulse generator) current–voltage curves successfully They also predict the same experimental tendencies of various device structural dimensions in practical engineering applications The electrothermal device simulation has shown its ability to predict a real device ESD/EOS event It will become a valuable tool to analyze device internal breakdown properties and find out optimized ESD/EOS conditions

8 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824