Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Integrated circuit, electronic device and esd protection therefor

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry (100) arranged to provide ESD protection to an external terminal (102) of the integrated circuit. The ESD protection circuitry (100) comprises: a thyristor circuit (200, 204) comprising a first bipolar switching device (200) operably coupled to the external terminal (102) and a second bipolar switching device (204) operably coupled to another external terminal (104), a collector of the first bipolar switching device (200) being coupled to a base of the second bipolar switching device (204) and a base of the first bipolar switching device (200) being coupled to a collector of the second bipolar switching device (204). A third bipolar switching device (214) is also provided and operably coupled to the thyristor circuit (200, 204) and has a threshold voltage for triggering the thyristor circuit (200, 204), the threshold voltage being independently configurable of the thyristor circuit (200, 204). The first and second switching devices (200, 204) are arranged so as to provide, when in use, a bidirectional snapback characteristic and a snapback voltage associated therewith.

Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

Abstract: For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.

Ultra high voltage GaN ESD protection device

Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I-V characteristics in NMOS devices

Abstract: A series of literature models originally devoted to the second breakdown trigger current I/sub t2/ in a grounded-gate NMOS transistor can further find promising potential in handling high-current I-V due to lateral bipolar snapback. This is achieved primarily by building significant linkage between bipolar current-gain /spl beta/-related parameters: 1) the collector-to-base junction voltage dependencies A/sub 1/ and A/sub 2/ of the medium-level injection /spl beta/ roll-off factor; 2) the high-level /spl beta/ roll-off factor A/sub 3/; and 3) the collector-to-base junction voltage dependencies A/sub 4/ and A/sub 5/ of the collector corner current at the onset of high-level /spl beta/ roll-off. The new parameters A/sub 1/ to A/sub 5/ enable a consistent I-V solution along with other existing six model parameters such as the substrate resistance R/sub sub/ and its conductivity modulation factor A/sub /spl tau//, the impact ionization coefficients K/sub 1/ and K/sub 2/, and the emitter series resistance R/sub e/ and collector series resistance R/sub c/. Parameter extraction except R/sub c/ is thoroughly performed using only the parametric analyzer, and opposed to the traditional procedure, impact ionization coefficients and current gains are all assessed without entering the snapback regime. Remarkably, not only excellent agreements are obtained, but also bipolar snapback I-V measured under the current pulsing condition can be separated into two distinct parts: medium- and high-level injection region. This is quite effective under R/sub e/=R/sub c/. Series resistance, although having very low value, is not to be absent under the high-level injection conditions.

Electrical fuse for integrated circuits

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out. The programmable transistor will then behave as a constant-on transistor during all subsequent read operations.