Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

Abstract: Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102 dc switching cycles.

Transistor circuits for switching high voltages and currents without causing snapback or breakdown

Abstract: A high voltage/high current switching circuit (200), without snapback or breakdown, comprises a first set of series-connected transistors that includes a plurality of transistors (MX30-MX63, MN0) to switch a high voltage without inducing snapback or breakdown ; and a second set of series-connected transistors that includes at least two transistors (MP2-MP3) to switch a high current. The first and second sets of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector (410) is connected to an output (Vep) of the first and second sets of series-connected transistors. The output (Vepup) of the voltage detector is coupled to the enabling means (500-2, 500-3).

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Abstract: A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only, mainly a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. It offers advantages of convenience in CAD implementation, high simulation speed, wider availability, and less convergence issues. The modeling approach has been used to investigate rise-time effects in TLP stress testing. The simulation, as well as measurement, demonstrated that the rising edge of TLP pulse affects snapback trigger voltage Vt1 not only in gate coupled NMOS but also grounded gate NMOS devices. It implies that the base transit time and the junction capacitance of parasitic BJT have impact on trigger voltage Vt1.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Abstract: Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-? transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.