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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


Papers
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Proceedings ArticleDOI
01 Sep 2016
TL;DR: In this article, an ESD empirical simulation flow for circuits containing snapback-based devices was described, where regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements.
Abstract: This work describes an ESD empirical simulation flow for circuits containing snapback-based devices. Regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements. Behavioral language VerilogA code has been used to add measured characteristics of the transistor at triggering voltage dependent on simulated gate voltage.

8 citations

Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this paper, an analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of "thermal runaway" under ESD conditions is presented.
Abstract: We present for the first time, analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of 'thermal runaway' under ESD conditions. The estimated It2 value from transient simulations has been correlated with the quasi-steady TLP data. A new regenerative bipolar turn-on induced failure model has been proposed and corroborated with experimental observations and failure analysis. We have also investigated the current crowding mechanism to understand the improvement in It2 value under gate and substrate biasing.

8 citations

Journal ArticleDOI
TL;DR: In this article, the dual implant superjunction (SJ) was used to achieve a 1.2-kV super junction in a reverse-conducting (RC) insulated-gate bipolar transistor (IGBT).
Abstract: This letter presents the dual implant superjunction (SJ) trench reverse-conducting (RC) insulated-gate bipolar transistor (IGBT) concept with two implanted SJ pillars in the drift region: one from the cathode side and another from the anode side. The proposed device is compatible with current manufacturing processes and enables a full SJ structure to be achieved in a 1.2-kV device, as alignment between the pillars is not required. Extensive technology computer aided design (TCAD) simulations have been performed and demonstrated that utilizing this dual implantation technique can result in a 77% reduction in turn-off losses for the full SJ structure, compared to a conventional RC-IGBT. The results show that any snapback in the ON-state waveform significantly increases the turn-off losses and only a deep SJ device (pillar $\text {gap} ) warrants the additional processing expense.

8 citations

Proceedings ArticleDOI
13 May 2003
TL;DR: In this paper, a generic design solution for the cascoded snapback NMOS that delivers robust operation and eliminates the requirement for an additional ESD implant is proposed, taking into account the non-linear effects of NMOS snapback, and providing, at a minimum, a phenomenological explanation of the observed trends resulting from the analysis of Si based experiments.
Abstract: The objective of this study is to find a generic design solution for the cascoded snapback NMOS that delivers robust operation and eliminates the requirement for an additional ESD implant. In addition, the research goal of this study is to understand the physical failure mechanism, taking into account the non-linear effects of NMOS snapback, and to provide, at a minimum, a phenomenological explanation of the observed trends resulting from the analysis of Si based experiments.

8 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824