Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

2.5-Dimensional simulation for analyzing power arrays subject to ESD stresses

Abstract: A new simulation-based methodology for analyzing the ESD performance of snapback multi-finger power arrays subject to ESD stress is developed and presented. The methodology utilizes a combination of a newly available 2.5-dimensional netlist extraction tool, ESD cell snapback compact model, and standard simulation CAD tools. Simulated snapback behavior and current distribution of power cells are demonstrated.

Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers As a result, potential harm to the ESD protection device (eg, from current crowding) is mitigated and the effectiveness of the device is improved

Devices and methods for calibrating and operating a snapback clamp circuit

Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.

Simulation of ultra thin film SOI transistors using a non-local ballistic model for impact ionisation

Abstract: To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.

Robust high current ESD performance of nano-meter scale DeNMOS by source ballasting

Abstract: “Strong Snapback” in DeNMOS transistors leads to weak ESD performance which is often represented by low It2 and strong die to die dependence. We report here the first experimental evidence that this can be controlled with introduction of source-resistance Rs. A new microscopic model has been analyzed to understand the physics of strong snapback and explain the experimental observations. Impact of current crowding phenomenon and role of adding a resistor across the source and ground has been broadly addressed in this paper. Also the current crowding phenomenon has been macroscopically modeled and a circuit model has been established.