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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors used a simplified model to determine the width dependence of the MOSFET substrate resistance and found that the normalized substrate current required for source turn-on predicted by this model is increased by an order of magnitude for wide-channel width transistors in agreement with measured data.
Abstract: Wide-channel MOSFETs have typically 10 to 30% lower breakdown voltages than narrow-width (W approximately=L) transistors and are less likely to exhibit clear snapback characteristics. These observations can be explained using a simplified model to determine the width dependence of the MOSFET substrate resistance. The normalized substrate current I/sub sub//W required for source turn-on predicted by this model is found to decrease by an order of magnitude for wide-channel-width transistors in agreement with measured data. This results in the observed decrease in breakdown voltage for wide-channel MOSFETs. >

6 citations

Proceedings Article
11 Sep 1994
TL;DR: In this paper, the authors used thermal and avalanche snapback points to predict when thermal runaway in a bipolar transistor is initiated and constructed the Safe Operating Area of the transistor in the case of a current and a voltage controlled base.
Abstract: Analytical calculations of thermal-and avalanche snapback points are given to predict when thermal runaway in a bipolar transistor is initiated. These snapback points are used to construct the Safe Operating Area of the transistor in the case of a current and a voltage controlled base.

6 citations

Patent
15 Jun 2016
TL;DR: In this article, a reverse conducting MOS gate-controlled thyristor provided by the invention can play a role of an electronic potential barrier when the current density is relatively low, so that the cell length of an N anode region is reduced; the effective area is reduced, and the snapback effect is inhibited by greatly improving an anode short-circuit resistance.
Abstract: The invention belongs to the field of power semiconductor devices, and particularly relates to a reverse conducting MOS gate-controlled thyristor and a fabrication method thereof. The novel reverse conducting MOS gate-controlled thyristor provided by the invention can play a role of an electronic potential barrier when the current density is relatively low, so that the cell length of an N anode region is reduced; the effective area is reduced; the snapback effect is inhibited by greatly improving an anode short-circuit resistance; a P floating region also carries out hole emission towards an N drift region along with a voltage increase, so that conductivity modulation is carried out and the snapback effect is inhibited. Meanwhile, due to additionally introduced P floating region in reverse conduction, a parasitic PNPN structure is passed in conduction; the thyristor is conducted when a current reaches a certain magnitude; and the novel reverse conducting MOS gate-controlled thyristor also has high current conduction capability in the reverse direction.

6 citations

Journal Article
TL;DR: In this article, a vertical trench electrode type EST has been proposed for improving snab-back effect, and the forward blocking voltage of the proposed device is 745V, while the conventional EST of the same size were no more than 633V.
Abstract: A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

6 citations

Patent
05 Apr 2013
TL;DR: In this paper, a voltage regulation circuit and a current controlled switch are used to modify a snapback voltage of a power clamp in a manner that enhances the power clamp's ability to handle ESD events.
Abstract: A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.

6 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824