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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


Papers
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Journal ArticleDOI
01 Oct 1991
TL;DR: In this article, the authors analyzed the phenomenon of the negative resistance portion of the output characteristic in MOSFETs and showed that the expansion of the base of the parasitic bipolar transistor provides the necessary basis for the understanding of the snapback mechanism.
Abstract: This paper analyses the phenomenon of snapback (negative resistance portion of the output characteristic) in MOSFETs. It shows that the expansion of the base of the parasitic bipolar transistor provides the necessary basis for the understanding of the snapback mechanism. It also offers simple criteria for the snapback triggering and sustaining which have been lacking to date.

5 citations

Proceedings ArticleDOI
01 Oct 1991
TL;DR: In this article, various issues in SOI (silicon-on-insulator) CMOS technology are reviewed and it is pointed out that from a device standpoint, the 'nice' properties of FD SOI MOSFETs, such as high saturation current and sharp subthreshold slope, are now overshadowed by unwanted floating substrate effects.
Abstract: Various issues in SOI (silicon-on-insulator) CMOS technology are reviewed. In particular, it is pointed out that from a device standpoint, the 'nice' properties of FD SOI MOSFETs, such as high saturation current and sharp subthreshold slope, are now overshadowed by unwanted floating substrate effects. The most serious of these is caused by the lateral bipolar, which causes snapback in long-channel devices. The snapback reduces to low BVDS in shorter-channel devices. There are indications that SOI may have a better BVDS than bulk for L >

5 citations

Patent
03 Aug 2012
TL;DR: In this article, the ESD protection device has a limited snapback behavior and has a well-tunable trigger voltage, but the trigger voltage is not adjustable by the user.
Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

5 citations

Journal ArticleDOI
Don L. Lin1
TL;DR: In this paper, the authors investigated the impact of VLSI scaling on the robustness of individual transistors against electrostatic discharge (ESD) damage and showed that if one relaxes the scaling in the device width dimension to κ 0.3, instead of κ, where κ is the scaling factor, the same or better ESD performance can be achieved as feature size shrinks.

5 citations

Proceedings ArticleDOI
09 May 2012
TL;DR: In this article, an approach of modeling the NPN BJT behavior of gate-grounded NMOS transistor is proposed for use as ESD clamp in IC I/O cells.
Abstract: Gate-grounded NMOS is often used as ESD protection for circuit design. The ESD behavior of the NMOS transistor is based on the snapback action of its parasitic, lateral NPN BJT. Modeling this behavior of NMOS devices is very important for design of ICs, because there are no standard models, which can be used for describing high current regions in the NMOS snapback characteristic. In this paper an approach of modeling snapback characteristic of NMOS device, intended for use as ESD clamp in IC I/O cells, is proposed. The modeled snapback characteristic is simulated and evaluated using PSPICE.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824