Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Physical modeling of off-state breakdown in power GaAs MESFETs

Abstract: We have investigated the physical mechanism of off-state breakdown in GaAs MESFETs that exhibited an initial breakdown voltage shift called “walkout” and snapback in I – V characteristics. From experiments using dual-gate MESFETs under various bias stress conditions, we attributed the origin of breakdown walkout to the change in electrical properties of the surface state at the gate edge. This was confirmed by experiments using newly developed open-gate FETs whose surface state was changed from an electron trap to a hole trap in the ungated region within about 0.4 μm from the gate edges. The change in surface-state properties can be explained by assuming electron injection from the gate metal into the oxide layer and the following surface Fermi-level dynamics. To verify our breakdown walkout model, we performed a two-dimensional simulation of gate–drain breakdown in GaAs MESFETs taking into account impact ionization, tunneling, and the proposed surface-state model. Our simulation can successfully describe the experimentally observed breakdown behavior, i.e., walkout and snapback.

Integrated circuit with semiconductor comprising a structure for protection against electrostatic discharges

Abstract: An integrated semiconductor circuit includes a protective structure for protection against electrostatic discharge. The protective structure is disposed between a terminal pad and the integrated semiconductor circuit and is connected to at least one busbar. The protective structure includes transistors of different types with reciprocal coupling of the collector terminals and base terminals to form a thyristor structure. Integrated vertical npn switching transistors are used as protective elements, the bases of which are driven by integrated pnp driving transistors. The gain factor of the driving transistors is small enough to avoid the triggering of the parasitic thyristor with undesirable snapback of the high current characteristic curve at the sustaining voltage. A buried layer having partial regions with a higher doping concentration than regions of the buried layer outside the partial regions. The buried layer has a very low resistance, which results in homogenization of the current flow in the event of breakdown. The turn-on voltage of the active protective element is additionally set by suitable selection of the base width of the driving transistors.

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

Abstract: The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures

Studies of decay and snapback effects on lhc dipole magnets

Abstract: 1LHC model magnets have dynamic field imperfections of various nature. Two effects of particular importance are field component decay during injection and ''snapback'' during the first few seconds of acceleration, which happens over typically 15 to 20 mT. The dynamic behaviour of the model magnets was measured as a function of several parameters in the operation cycle and powering history. We demonstrate how the systematic variation of only one single operation cycle parameter can affect the behaviour of the sextupole component.

Low Voltage NPN with Low Trigger Voltage and High Snap Back Voltage for ESD Protection

Abstract: An area-efficient, low voltage ESD protection device ( 200 ) is provided for protecting low voltage pins ( 229, 230 ) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region ( 216 ) and P+ base region ( 218 ) formed on opposite sides of an N+ emitter region ( 217 ) with separate halo extension regions ( 220 - 222 ) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It 2 ) and set the snapback voltage (Vsb) and triggering voltage (Vt 1 ) at the desired level.