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Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.


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Proceedings Article
09 Nov 2010
TL;DR: Simultaneous optimization of LDD and anti-punch-through implant conditions for ESD performance of very large width silicided output driver nMOSFET without snapback mode of operation is reported in this article.
Abstract: Simultaneous optimization of LDD and Anti-punch-through implant conditions for ESD performance of very large width silicided output driver nMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulse width are detailed.

4 citations

Patent
15 Jul 2015
TL;DR: In this paper, a reverse-conducting insulated gate bipolar translator (RC-IGBT) was proposed to prevent the snapback effect in power semiconductor technology, in particular in particular to the power semiconductors.
Abstract: The invention relates to the power semiconductor technology, in particular to an RC-IGBT (reverse-conducting insulated gate bipolar translator) capable of inhibiting a snapback effect. A main method of the RC-IGBT comprises steps as follows: a metal resistor with proper resistance is produced between electrode contacts of a P-type collector region and an N-type collector region, when the device is connected forwards, the current IF flows through the metal resistor R and produces voltage drop IFR on the metal resistor, the voltage difference is produced between the P-type collector region and an N-type buffer layer, and if the IFR is larger than the forward connection voltage drop of a PN junction, the PN junction is connected forwards to be in an IGBT working mode, so that the snapback effect is effectively inhibited. The RC-IGBT has the benefits that the RC-IGBT has the excellent capacity of inhibiting the snapback phenomenon under the condition that the process complexity is not increased excessively, and meanwhile, other performance parameters of the RC-IGBT cannot be affected.

4 citations

Proceedings ArticleDOI
01 Dec 1982
TL;DR: In this article, a model for the drain I-V characteristics in the snapback region is proposed, incorporating conductivity modulation that predicts linear relationships between the substrate and the remote-junction collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased pn junction also increase with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics in the snapback region is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the remote-junction collection currents and the drain current in this region of operation. Experimental results agree well with the models.

4 citations

Journal ArticleDOI
Hu Fei1, Song Limei1, Zhengsheng Han1, Du Huan1, Jiajun Luo1 
TL;DR: A base resistance controlled thyristor with semi-superjunction (Semi-SJ BRT) is proposed in this paper and, when the pillar doping level is higher than 1.0 × 1015 cm−3, snapback-free can be realized and turn-off loss can be reduced by 22.28%.
Abstract: A base resistance controlled thyristor with semi-superjunction (Semi-SJ BRT) is proposed in this paper. The highly doped P-pillar in drift region extracts injected holes into thyristor, then hole current density in thyristor will be improved and parasitic transistor is significantly suppressed. Meanwhile, highly doped drift region reduces drift resistance, then thyristor trigger current is enhanced. Snapback is greatly suppressed. In addition, much more minority carriers will be extracted due to charge coupling effect in drift region. Turn-off loss is reduced and trade-off performance is improved. Numerical simulation results show that, when the pillar doping level is higher than 1.0 × 1015 cm−3, snapback-free can be realized and turn-off loss can be reduced by 22.28%.

4 citations

01 Jan 2008
TL;DR: In this paper, an enhancement to the modeling of the "snapback" in MOS transistors for ESD simulation is presented, which uses industry standard models and includes all major physical effects characteristics of snapback.
Abstract: An enhancement to the modeling of the ‘snapback’ in MOS transistors for ESD simulation is presented. The new model uses industry standard models and includes all major physical effects characteristics of snapback. The MOS snapback model is enhanced by partitioning the Drain and Source junctions so that only a portion of them is included in the parasitic BJT. The comparison of simulation and measured data of a Grounded-Gate NMOS shows good agreement for both positive and negative drain voltage stresses. Simulation of the base current of the parasitic bipolar shows significant improvement as well.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202227
202127
202033
201939
201824