Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
Papers published on a yearly basis
Papers
More filters
01 Jan 1998
4 citations
Patent•
31 May 2001TL;DR: In this article, a magnetic snapback sensor circuit for sensing current transients imposed on the snapback circuit including a current conductor loop, a conductor carrying current from a SNAP and intersecting with the conductor loop for magnetically generating a current in the loop, and a current detector circuit for generating an output responsive to the current flowing in a loop induced by a current transient.
Abstract: A magnetic snapback sensor circuit for sensing current transients imposed on the snapback circuit including a current conductor loop; a conductor carrying current from a snapback circuit subject to current transients and intersecting with the conductor loop for magnetically generating a current in the loop; and a current detector circuit for generating an output responsive to the current flowing in the loop induced by a current transient.
4 citations
Journal Article•
TL;DR: To reduce the cycle time and the cost of the design of ESD tolerant over-voltage I/O cells, a methodology for pre-silicon ESD protection optimisation is described, based on Technology Computer Aided Design (TCAD) and compact (circuit level) simulation studies.
4 citations
Patent•
12 Mar 2014
TL;DR: In this article, a strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with an ESD (Electro-Static Discharge) protective function is described.
Abstract: The invention relates to the electronic technology and specifically relates to a strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with an ESD (Electro-Static Discharge) protective function. The LIGBT device isolates an N-type epitaxial layer 3 by an isolation area 13 into two parts; a first P-type well region 4 and an N-type well region 6 are arranged in the N-type epitaxial layer 3 at one side of the isolation area 13; a second P-type well region 5 is arranged in the N-type epitaxial layer 3 at the other end of the isolation area 13; and a second N-type heavy doping region 22 and a third N-type heavy doping region 23 which are independent with each other are arranged in the second P-type well region 5. The strong anti-latch-up controllable LIGBT device disclosed by the invention has the beneficial effects that on an no-power condition, current is leaked by a parasitic SCR (Semiconductor Control Rectifier), so that ESD ability is very strong; under a power-on state, the parasitic SCR of the LIGBT cannot be started and snapback is not generated, so that maintaining voltage higher than breakdown voltage is achieved, and therefore, the anti-lath-up ability is very strong. The strong anti-latch-up controllable LIGBT device disclosed by the invention is especially suitable for the LIGBT device used for ESD protection.
4 citations