Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer

Abstract: This paper presents a novel technique to eliminate non-simultaneous triggering effects in finger-type ESD protection transistor using SiGe heterojunction buried layer structures. It is confirmed that lower snapback voltage and maximum lattice temperature are obtainable in the new structure based on device simulation. As a result, current localization and lattice overheating of a finger-type protection transistor caused by process variations can be avoided in this structure.

Dual-direction Isolated NMOS-SCR device for system level ESD protection

Abstract: A novel dual-direction device is suggested for system level ESD protection. The device combines both a deep NWELL isolated snapback NMOS and a lateral SCR structure using a shared regions approach. ESD pulse operation of the device has been experimentally studied for a 0.35 mum 5 V CMOS process by numerical simulation and then experimentally validated for system level IEC specification requirements.

ESD protection cluster and method of providing multi-port ESD protection

Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Abstract: Developing an electrostatic discharge (ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor (CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

A pad ICIM model for EMC immunity simulation

Abstract: Accurate prediction of the response of integrated circuit (IC) to electromagnetic interferences (EMI) is increasingly important. In this paper, a precise integrated circuit immunity model (ICIM) of electrostatic discharge (ESD) protection pads is developed and validated. The model consists of a parasitic RC network model and an ESD snapback model. The parameters of the physically-based parasitic RC network model are extracted from specifically designed structures with ESD pads and validated by S-parameter measurement data. The combined model is able to predict the immunity level more precisely and better support the immunity simulation of circuit under direct power injection (DPI) test.