Snapback

About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.

Novel trench gate field stop IGBT with trench shorted anode

Abstract: A novel trench field stop(FS) insulated gate bipolar transistor(IGBT) with a trench shorted anode(TSA)is proposed. By introducing a trench shorted anode, the TSA-FS-IGBT can obviously improve the breakdown voltage. As the simulation results show, the breakdown voltage is improved by a factor of 19.5% with a lower leakage current compared with the conventional FS-IGBT. The turn off time of the proposed structure is 50% lower than the conventional one with less than 9% voltage drop increased at a current density of 150 A/cm~2. Additionally,there is no snapback observed. As a result, the TSA-FS-IGBT has a better trade-off relationship between the turn off loss and forward drop.

A snapback-free reverse conducting IGBT with recess and floating buffer at the backside

Abstract: We propose two novel ways to alleviate the reverse conducting insulated gate bipolar transistor (RC-IGBT) snapback phenomenon by introducing the floating field stop layer with a lightly doped p-floating layer and recess structure at the backside. The floating field stop layer is submerged in the N-drift region and located several micrometers above the P+ anode region, which would not degrade the blocking capability but can suppress the snapback phenomenon effectively. When the collector length exceeds 100 μm, the snapback voltage ΔVSB of the floating field stop RCIGBTwith the p-floating layer can be less than 0.5V. Furthermore, the recess structure at the backside can separate the N+ short and P+ anode region, which will be beneficial to eliminate the snapback. Finally, an RC-IGBTwith a floating buffer layer and recess at the backside is proposed. Compared to the RC-IGBT featuring an oxide trench between the N+ short and P+ anode, the proposed one has utilized the simple recess structure to replace the costly oxide trench and achieved the identical characteristics simultaneously.

Protection circuit against electrostatic discharge with two capacitors

Abstract: The ESD protection circuit includes an ESD bypass device (223) incorporating an NMOS and PMOS transistor for bypassing the ESD current. A capacitor-couple circuit (222) couples a portion of voltage to the ESD bypass device, and a potential levelling device (224) incorporates two diodes for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the thinner gate oxide of the internal circuit (23) of the IC.

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

Abstract: This paper presents the device-level electrostatic discharge (ESD) robustness improvement for integrated vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate-voltage dependence of the second breakdown current (It2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Stand-alone triggering structure for ESD protection of high voltage CMOS

Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.