Topic
Snapback
About: Snapback is a research topic. Over the lifetime, 742 publications have been published within this topic receiving 8225 citations.
Papers published on a yearly basis
Papers
More filters
2 citations
01 Jul 2019
TL;DR: In this paper, a Diode Triggered Silicon Controlled Rectifier (DTSCR) model is proposed to simulate the I-V characteristics of a DTSCR with snapback.
Abstract: A Diode Triggered Silicon Controlled Rectifier (DTSCR) is modeled. This DTSCR compact model is able to simulate the DTSCR’s I-V characteristics with snapback. Overshoot related parameters in this model also reproduces the overshoot phenomenon in transient simulation. Simulation of non-linear resistivity in the high current region is modeled based on the electro-thermal behavior and velocity saturation. This model is not only able to simulate quasi-static I-V under typical ESD stresses, but can predict ESD failure with arbitrary input ESD waveforms.
2 citations
01 Jan 2018
2 citations
TL;DR: A 2D simulation approach that takes into account the 3D effects of electro-thermal instability during electrostatic discharge (ESD) operation, is presented.
2 citations
Patent•
03 Mar 2000
TL;DR: In this paper, the authors proposed to increase the electrostatic protection capability by making the concentration of a well below a channel formation region of an N-type MOS transistor included in an electrostatic protective element circuit lower than that of a low-density P-type impurity region having a concentration of 1×1016 (atoms/cm3) or about which is for improvement of a snapback characteristic.
Abstract: PROBLEM TO BE SOLVED: To increase the electrostatic protective capability by making the concentration of a well below a channel formation region of an N-type MOS transistor included in an electrostatic protective element circuit lower than that of a well below a channel formation region of an N-type MOS transistor included in other circuit than the electrostatic protective element circuit. SOLUTION: On a P-type semiconductor substrate 1, a P-type well 2 having a concentration of 3×1017 (atoms/cm3) or about is formed. Right under a gate electrode 6, a low concentration P-type impurity region 3 having a concentration of 1×1016 (atoms/cm3) or about which is for improvement of a snapback characteristic and has a lower a concentration than the P-type well 2, and a P-type impurity region 4 for adjusting Vt having the a concentration of 5×1017 (atoms/ cm3) or about which is higher than the concentration of the lower density P-type impurity region 3, are formed. Moreover, a gate oxide film 5, a gate electrode 6, and the source and the drain 7 are formed to build an N-type MOS transistor 20. As a result, the electrostatic protective capability can be increased.
2 citations